Introduction to Timing Constraints
In digital synchronous designs, sequential elements (like flip-flops) require stable input signals during a specific window around the active clock edge to latch data correctly. This window is defined by two fundamental constraints: Setup Time ($T_{setup}$) and Hold Time ($T_{hold}$).
Mathematical Timing Equated Bounds
Setup Check: T_launch + T_clk2q + T_dp < T_capture + T_clk - T_setup
Hold Check: T_launch + T_clk2q + T_dp > T_capture + T_hold
Why Setup and Hold Violations Occur
Setup violations occur when the data path delay ($T_{dp}$) is too long, meaning the signal arrives too late. This can be caused by high logic levels, high fan-out, or routing congestion.
Hold violations occur when the data path delay is too short, meaning the signal changes too quickly and overwrites the active state. This is often caused by fast paths (short routing) or significant clock skew.
Timing Closure Remediation Strategies
- Fixing Setup Violations: Reduce combinational logic depth, perform gate sizing (using faster cells), clone high fan-out cells, or apply useful clock skew.
- Fixing Hold Violations: Insert delay buffers on the violating paths to delay the data transition, or size down cells to increase delay without altering setup margins.