• • Boolean algebra, logic gates, and combinational circuits.

  • Flip-flops, registers, counters, and sequential logic.

  • FSM basics (Mealy & Moore) and state encoding techniques.

  • Hands-on lab: Design & simulate basic digital circuits.

  • Introduction to Verilog, module structures, and data types.

  • FSM implementation and debugging in Verilog.

  • Timing concepts: setup/hold time, metastability, CDC.

  • Hands-on lab: Implement & simulate FSM and basic RTL designs.

• • Introduction to SystemVerilog: Data types, OOP Concepts, and Interfaces.

  • Assertions (SVA) & Functional Coverage for Verification Efficiency.

  • Testbench Architecture: Transaction-Based Modeling & UVM Basics.

  • Lab Task: Implement SystemVerilog Assertions & Coverage in a testbench.

    • Introduction to HDL, RTL vs. Behavioral Coding, and ASIC/FPGA Flow.

    • Verilog constructs: Data types, operators, and procedural blocks.

    • Combinational & Sequential Circuits (MUX, FSM, Counters, Registers).

    • Lab Task: Implement and simulate basic logic circuits in Verilog.

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    • Tasks, Functions, Generate Statements, and Parameterized Designs.

    • Finite State Machine (FSM) Design & Optimization in Verilog.

    • Testbench Development: Stimulus Generation, Monitors, and Assertions.

    • Lab Task: Write a self-checking testbench for a basic digital circuit

  • Verification methodologies: Directed, Random, and Constraint-Based Testing.

  • Low-Power Design Verification (Clock Gating, Power Gating).

  • Industry-standard Verification Flow & Debugging Techniques.

    Final Project: Complete an RTL design & verification cycle with reports.

• • Basics of Verilog: Data types, procedural/continuous assignments.

  • Writing combinational & sequential circuits for verification.

  • Testbench basics: Stimulus generation, initial & always blocks.

  • Lab Task: Write and simulate testbenches for logic gates & flip-flops.

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  • Writing modular testbenches with tasks and functions.

  • Creating self-checking testbenches with if, case, and loops.

  • Debugging techniques: Waveform analysis & error detection.

  • Lab Task: Develop a self-checking testbench for an FSM.

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  • Testbench components: Drivers, Monitors, and Scoreboards.

  • Assertions (SVA) and functional coverage techniques.

  • File I/O and memory modeling for verification.

  • Lab Task: Implement assertions and functional coverage in a testbench.

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  • Verification methodologies: Directed vs. random testing.

  • Debugging timing issues & race conditions.

  • Industry case study: Verifying a simple CPU or protocol

    Final Project: Verify a real-world RTL design & generate a verification report.

•     Introduction to UART protocol: TX, RX, baud rate, framing, and parity.

  • Reviewing the UART RTL design and defining verification requirements.

  • Setting up the simulation environment and writing a basic testbench.

  • Lab Task: Develop a simple UART transmitter and receiver testbench.

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  • Creating directed and constrained-random test scenarios.

  • Implementing transaction-level stimulus (packets, error injection).

  • Developing monitors and scoreboards for self-checking verification.

  • Lab Task: Write a testbench to verify UART frame formats and error cases.

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  • Implementing SystemVerilog Assertions (SVA) for protocol checks.

  • Writing functional coverage to measure verification completeness.

  • Debugging timing violations and race conditions.

  • Lab Task: Add functional coverage and assertions to the testbench.

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  • Running simulations, debugging failures, and optimizing the testbench.

  • Generating verification reports with coverage analysis.

  • Industry best practices: Regression testing and reusable testbenches.

  • Final Project Submission: Complete UART verification and submit a final report.

✅ Lab Access: Available throughout the course for hands-on practice.
🏆 Certification: Issued upon successful completion of the project and final review. 

Sample Course Certificate