Fundamentals of Electronic Devices & Power Systems
Thevenin’s & Norton’s Theorems in Circuit Analysis
Semiconductor Physics: Atomic Structure, Electron Configuration, Doping Techniques, Diode Biasing & VI Characteristics
MOSFET Operations: Modes of Functionality & Voltage-Current Characteristics
CMOS-Based Function Realization
Stick Diagrams & Layout Representation
Advanced MOSFET Effects: Body Effect, Channel Length Modulation, Punch-Through, Subthreshold Conduction, and Drain-Induced Barrier Lowering (DIBL)
Semiconductor Fabrication Process: Cleanroom Standards, Wafer Manufacturing, Oxidation, Diffusion, Ion Implantation & Lithography
Evaluation & Knowledge Testing

• Introduction to Linux
• Command-Line Operations
• File Management and Processes
• Text Editors (VI, GVIM, etc.)
• Text Manipulation Commands
• Network Operations and Utilities
• Special Keystrokes and Shortcuts

• Number System, Boolean Algebra,
• SOP and POS, K-Map,
• Combinational circuits, Sequential
circuits,
• Finite State machines,
• Frequency Division,
• Setup and Hold time checks,
• Advance Design Issues: Metastability,
Noise Margins, Power, Fanout, Timing
Considerations,

SV Testbench Architecture, Verilog vs System Verilog, SV Data types: 2 state vs 4 state variables, Dynamic Arrays, Associative Arrays, and its Usage.

Features of TCL & Applications
TCL Commands & Syntax
Variables & Data Types
Arithmetic Expressions & Operators
Comments, Identifiers & Reserved Words
Control Structures (Decisions & Loops)
Arrays, Strings & File I/O Operations
Procedures & Modular Scripting
Scripting Exercises (Basic to Advanced)
Tool-Specific Scripting 

• Introduction to Python
• Control Structures and Functions
• Data Structures and File Handling
• Object-Oriented Programming (OOP) in Python
• Python for Automation in VLSI
• Data Processing and Visualization
• Regular Expressions and Debugging
• Advanced Topics and Assignmnets

Verilog HDL

• ASIC Flow, Module, declaration and Instantiation, Components of
simulation, Procedural blocks, Lexical convections.
• Data types, Module Parameters, Operators, Primitives, Functional.
representation in Verilog.
• Arrays, Memories, System tasks, compiler Directives, Continuous and
Procedural Assignments, Examples of Blocking and Non-blocking statement.
• Race Condition, Timing Controls Sequential and Parallel Blocks, Conditional Statements, loops Statements.
• Task, Functions, Difference between task and Function.

Strings, Unions, Structures, Enumerated data Types, Events.

SV Interfaces: Interface ports, Mod ports, Clocking blocks, Virtual Interface, Program blocks.

SV Class, Inheritance, this operator, super operator, shallow copy, deep copy, parameterized classes, typedef classes, polymorphism, abstract class, encapsulation, dynamic casting, scope resolution operators.

IPC: Event, Mailbox, Semaphores Randomization & Constraints: Basics, specifying constraints, methods in constraints, random stability, random sequences, and random case.

Introduction, Advantage and types of assertions, Sequence & property, writing assertion using operators & system tasks.

Code coverage, functional coverage, cover groups, cover points, cover bins, cross coverage, coverage options & methods.

Limitations of SV testbench, Migrating from SV to UVM, UVM Architecture, UVM Class Hierarchy.

UVM Phase categorization, UVM Reporting.

TLM 1.0, TLM 2.0, Examples.

UVM Field Macros, Factory registration, create method, factory override.

UVM config database, construction of UVC, sequence generation, Sequences, Virtual Sequencer, Virtual Sequences.

• AXI Protocol Verification
• UART Controller Verification
• Memory Controller Verification (DDR/SDRAM)
• RISC-V Processor Verification
• I2C Bus Verification