Verilog HDL
• ASIC Flow, Module, declaration and Instantiation, Components of
simulation, Procedural blocks, Lexical convections.
• Data types, Module Parameters, Operators, Primitives, Functional.
representation in Verilog.
• Arrays, Memories, System tasks, compiler Directives, Continuous and
Procedural Assignments, Examples of Blocking and Non-blocking statement.
• Race Condition, Timing Controls Sequential and Parallel Blocks, Conditional Statements, loops Statements.
• Task, Functions, Difference between task and Function.