Fundamentals of Digital Design

• Boolean algebra, logic gates, and combinational circuits.

• Flip-flops, registers, counters, and sequential logic.

• FSM basics (Mealy & Moore) and state encoding techniques.

• Hands-on lab: Design & simulate basic digital circuits.

RTL Design & Verilog Coding

• Introduction to Verilog, module structures, and data types.

• FSM implementation and debugging in Verilog.

• Timing concepts: setup/hold time, metastability, CDC.

• Hands-on lab: Implement & simulate FSM and basic RTL designs.

Introduction & Floorplanning

• Overview of ASIC Design Flow & Role of Physical Design.

• Floorplanning: Macro placement, IO pad planning, aspect ratio.

• Power planning: Power mesh, IR drop, and electromigration.

• Hands-on lab: Floorplan a simple design with power routing.

Placement & Clock Tree Synthesis (CTS)

• Standard cell placement, congestion analysis, and legalization.

• Clock Tree Synthesis (CTS): Skew, latency, and clock buffers.

• Timing concepts: Setup/Hold time, Clock Domain Crossing (CDC).

• Hands-on lab: Placement & CTS using industry-standard tools.

Routing & Timing Closure

• Global & detailed routing, DRC checks, metal layer optimization.

• Timing closure: STA (Static Timing Analysis), ECO, and fixing violations.

• Signal integrity: Crosstalk, noise, shielding, and IR drop analysis.

• Hands-on lab: Routing & timing analysis on a real-world design.

Physical Verification & Signoff

• DRC, LVS, and Antenna Rule checks using foundry rule decks.

• Parasitic extraction & post-layout STA (RC delay analysis).

• Power optimization techniques: Dynamic/static power reduction.

• Final project: Complete a design from floorplanning to signoff.

Setup & Floorplanning

• Introduction to ASIC design flow & project overview.

• Design setup: Library selection, constraints, and tool environment.

• Floorplanning: Macro placement, power planning, and congestion analysis.

• Lab Task: Perform floorplanning and power planning on a real design.

Placement & Clock Tree Synthesis (CTS)

• Placement optimization, legalization, and congestion removal.

• Clock Tree Synthesis (CTS): Clock buffers, skew, and latency analysis.

• Timing analysis: Setup/Hold time, IR drop, and EM checks.

• Lab Task: Run placement and CTS on a standard cell design.

Routing & Timing Closure

• Global & detailed routing, DRC checks, and parasitic extraction.

• Timing closure strategies: ECO, SI analysis, and fixing violations.

• Power optimization: Clock gating, multi-Vt cells, and dynamic/static power.

• Lab Task: Perform routing, DRC/LVS, and timing analysis.

Signoff & Certification

• Physical verification: DRC, LVS, ERC, and Antenna Rule checks.

• Final STA: Post-layout timing verification and power analysis.

• Report generation & review for certification eligibility.

• Final Project Submission: Complete a design from floorplanning to signoff.

✅ Lab Access: Available throughout the course for hands-on practice.
🏆 Certification: Issued upon successful completion of the project and final review.

Sample Course Certificate