Fundamentals of Electronic Devices 
Diode Biasing & VI Characteristics
MOSFET Operations: Modes of Functionality & Voltage-Current Characteristics
CMOS-Based Function Realization
Stick Diagrams & Layout Representation
Advanced MOSFET Effects: Body Effect, Channel Length Modulation, Punch-Through, Subthreshold Conduction, and Drain-Induced Barrier Lowering (DIBL)
Semiconductor Fabrication Process: Cleanroom Standards, Wafer Manufacturing, Oxidation, Diffusion, Ion Implantation & Lithography
Evaluation & Knowledge Testing

• Number System, Boolean Algebra, SOP and POS, K-Map
• Combinational circuits
• Sequential circuits
• Finite State machines
• Frequency Division
• Setup and Hold time checks
• Advance Design Issues: Metastability, Noise Margins, Power, Fanout, Timing Considerations
• FIFO Depth Calculation
• Assessment and Quizzes
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• Overview of Linux
  Shell Command Operators
  File Management & Operations
  Process Handling & Management
  Text Editors & Editing Tools
  Text Processing & Manipulation
  Networking & Communication Commands
  Keyboard Shortcuts & Special Keystrokes
  Evaluations & Quizzes

Introduction to Verilog
Applications of Verilog HDL
Verilog HDL Language Concepts
Verilog Language Basics & Constructs
Data Types: Nets, Registers & Arrays
Verilog Operators: Logical, Bitwise, Reduction, Concatenation, Conditional, Relational, Arithmetic, Shift, Equality, Operator Precedence
Types of Assignments: Continuous, Inter/Intra, Blocking & Non-Blocking, Execution Branching, Tasks & Functions
Finite State Machine (FSM): Structure, Moore vs. Mealy, FSM Coding Styles, Registered Outputs
Assessment & Quizzes

Features of TCL & Applications
TCL Commands & Syntax
Variables & Data Types
Arithmetic Expressions & Operators
Comments, Identifiers & Reserved Words
Control Structures (Decisions & Loops)
Arrays, Strings & File I/O Operations
Procedures & Modular Scripting
Scripting Exercises (Basic to Advanced)
Tool-Specific Scripting 

ASIC Design Flow & Role of Synthesis
Synthesis Flow
Writing Timing Constraints (SDC Format)
Design Constraints & Optimization
Synthesis Process
Report Analysis & Netlist Generation

• Formal Verification
• Understanding & Matching compare points
• Debugging non equivalent points
• What-If Analysis

Introduction to Physical Design: The process of converting a synthesized netlist into a manufacturable layout while optimizing for performance, power, and area (PPA).

Physical Design Flow: Data Preparation → Floorplanning → Placement → Clock Tree Synthesis (CTS) → Routing → Sign-Off.

Data Preparation – Required Files:

• Netlist: Gate-level representation of the design.
• SDC: Defines timing constraints (clock, delays, false paths).
• Libraries (.lib): Standard cell timing and power data.
• Technology Files: Design rules, metal layers, routing constraints.
• TLU+: Parasitic models for accurate timing analysis.

Sanity Checks:

Floorplanning Objectives: Defining an optimal chip layout to enhance performance, minimize congestion, and improve manufacturability. Key Aspects of Floorplanning: Determining core area, power distribution, signal integrity, and routability. Types of Floorplans: Rectangular and Rectilinear floorplans based on design complexity and area constraints. Die Size Estimation: Calculating die area using Core Utilization (ratio of standard cell area to total die area) and Aspect Ratio (height-to-width ratio for balanced layout). I/O Placement: Strategically positioning I/O pads for minimal wirelength and efficient signal routing. Macro Placement: Guidelines for placing memory blocks, PLLs, and IP cores to optimize performance and minimize congestion. Channel-Width Estimation: Determining routing space between macros and standard cells to avoid congestion and improve connectivity.

Power Routing Objectives: Ensuring a robust and efficient power delivery network (PDN) to meet power integrity and reliability requirements. Power Distribution Structures: Implementing Power Rings, Straps, and Follow-Pin/Standard Cell Rails for effective power distribution. Metal Stack Information: Understanding metal layers, resistivity, and current-carrying capacity for optimized power routing. Power Planning Methodology: Defining power grid structures, budgeting power requirements, and integrating power-aware design techniques. IR Drop Analysis: Evaluating voltage drops across the power network to prevent functional failures and timing degradation. Types of Power Consumption: Dynamic power (switching activity), Static power (leakage currents), and Short-circuit power. Importance of Low-Power Design: Reducing power dissipation for energy efficiency, thermal management, and enhanced battery life. Low-Power Techniques: Clock gating, power gating, multi-Vt design, voltage scaling, and dynamic voltage and frequency scaling (DVFS). Electromigration (EM) Analysis: Assessing current density in metal interconnects to prevent reliability failures and long-term degradation of the chip.

Placement Objectives: Ensuring optimal cell arrangement for improved performance, routability, and power efficiency. Types of Placement: Standard cell placement, macro placement, and mixed-size placement. Pre-Placement Steps: Insertion of End-cap cells, Tap cells, and I/O Buffers to prevent design rule violations. Placement Optimization: Minimizing wirelength, reducing congestion, and balancing power distribution. Congestion Analysis: Identifying and resolving congestion hotspots for smoother routing. Timing Analysis During Placement: Evaluating setup and hold timing to ensure timing closure. Tie-Cell Insertion: Connecting floating gates of standard cells to avoid leakage. High-Fanout Net Synthesis (HFS): Buffering high-fanout nets to improve signal integrity. Scan Chain Reordering: Optimizing scan chain connections for minimal routing overhead. Path Grouping & Bound Creation: Defining logical groupings and placement constraints for improved timing and congestion management.

STA Overview & Key Concepts: Understanding Static Timing Analysis (STA) and its role in VLSI design. Fundamental Timing Checks: Setup and hold time analysis to ensure reliable circuit operation. Timing Constraints (SDC): Writing and interpreting Synopsys Design Constraints (SDC) for accurate timing analysis. Timing Corners & Variations: Handling process, voltage, and temperature (PVT) variations for robust timing closure. Timing Report Analysis: Extracting and interpreting critical path delays, slack values, and violations.

Optimization Techniques: Identifying and resolving timing violations using best industry practices. Common Causes of Timing Violations: Understanding high fan-out nets, clock skew, excessive logic depth, and congestion. Fixing Setup & Hold Violations: Strategies like cell upsizing, buffer insertion, path reordering, and logic restructuring. Pre-CTS Optimization: Addressing setup violations before Clock Tree Synthesis (CTS) to improve overall timing closure.

Clock Tree Synthesis (CTS) Objectives: Ensuring balanced clock distribution with minimal skew and latency. Types of Clock Trees: H-Tree, X-Tree, Fishbone, and Mesh-based clock structures. CTS Constraints: Defining clock constraints, insertion delay, skew, and transition limits. Clock Tree Construction: Implementing an optimized clock tree while meeting design constraints. Post-CTS Analysis: Evaluating clock tree performance, skew, and timing reports. Post-CTS Optimization: Resolving setup and hold violations through buffer insertion, gate sizing, and delay balancing.

Routing Goals and Stages: Overview of routing objectives and challenges in VLSI design. Routing Phases: Global Routing, Track Assignment, and Detailed Routing. Routing Strategies: Exploring various routing options for optimal performance. Violation Fixing: Addressing DRC and LVS violations with effective debugging techniques. Post-Route Optimization: Enhancing routing quality after initial implementation. Challenges & Best Practices: Identifying common routing issues and applying industry guidelines for optimal results.

Post-Layout STA Analysis: Performing Static Timing Analysis using SPEF for accurate parasitic extraction. Multi-Mode Multi-Corner (MMMC) STA: Ensuring timing robustness across different operating modes and process corners. Timing Variability Considerations: Incorporating derating factors, Process-Voltage-Temperature (PVT) variations, and On-Chip Variation (OCV) effects. Signal Integrity Analysis: Evaluating Crosstalk and its impact on timing and functionality.

Scan Chain, ATPG, BIST Test Structures, Fault Modeling, MBIST

DRC, LVS & Parasitics
Layout Verification, IR Drop Analysis,
Electromigration Checks

What is ECO, Types of ECO, Timing & Functional ECO, Performing the ECO placement and routing.

Physical Verification (DRC, LVS), IR drop analysis, Electro-Migration Analysis.

• 7nm &14nm Projects will be given converging Netlist to GDS II flow. 
• Various projects that will allow the students to understand the intricacies of implementation for the minimum area, low power, high performance.
• The method of execution will be similar to typical block level Physical Design work/project in the industry.
• Block level input database will be given and the participant has to deliver GDS II, after cleaning all the issues during sign-off checks.