What is metastability in digital circuits and how is it resolved?
Metastability is an unstable state where a flip-flop fails to settle into a stable logical high or low within the clock cycle, usually triggered by setup or hold violations. It is resolved by employing multi-stage synchronizers to allow the signal to settle.
The Physics of Metastability
When setup or hold times are violated at a bistable element (like a flip-flop), the internal feedback loop cannot resolve the input voltage level to a definitive high (VDD) or low (GND) before the active clock edge. Instead, the output enters a temporary, unstable state between logical boundaries—metastability.
Mean Time Between Failures (MTBF)
Metastability cannot be 100% prevented, but its probability of failure can be reduced to negligible rates. The reliability of a synchronizer is measured using Mean Time Between Failures (MTBF), calculated as:
MTBF = e^(s * T_settle) / (f_clk * f_data * C)
Where s and C are physical parameters of the technology, f_clk is the clock frequency, f_data is the asynchronous transition rate, and T_settle is the available settling time.
Practical Mitigations
- Multi-stage Synchronizers: Cascading two or three flip-flops on the capture domain to increase T_settle and boost MTBF to thousands of years.
- Advanced Cell Design: Using specialized, high-gain synchronizer flip-flop cells with very low internal settling constants.
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