Understanding Floorplanning in Physical Design

Introduction to Understanding Floorplanning in Physical Design

Understanding the details of Understanding Floorplanning in Physical Design is essential for front-end verification, DFT testing, or backend timing closure in modern sub-micron silicon processes.

This daily knowledge byte offers concise definitions, architectural outlines, and practical design solutions to support your engineering career.

What floorplanning actually decides

Floorplanning is the first physical step after synthesis, and it is the step with the longest shadow. Everything downstream — placement legality, clock tree depth, routability, IR drop, even whether timing can close at all — is constrained by decisions made here. A netlist that is impossible to route was usually made impossible at floorplan, not at routing.

Concretely, floorplanning sets the die size and shape, fixes the location of every hard macro, defines the power delivery skeleton, places the I/O pins, and reserves the blockages and halos that keep standard cells out of the places they must not go.

Core utilisation and die area

Core utilisation is the fraction of the core area occupied by standard cells before placement optimisation begins. It is the single most consequential number in the floorplan.

• Too high (say 85–90%+) and the placer has nowhere to put buffers. Timing optimisation, clock tree synthesis and hold fixing all need spare sites; without them the tool either fails to close timing or produces severe congestion.
• Too low (say below 50%) and you are paying for silicon you do not use. Wire lengths also grow, which costs both timing and power.
• Typical starting points sit around 65–75% for a block with moderate macro content, adjusted after the first placement and congestion run.

Utilisation is not a target to hit once — it is a dial you turn based on what the first trial placement tells you about congestion and timing.

Aspect ratio and block shape

The aspect ratio (height divided by width) determines how the block’s internal connectivity maps onto physical distance. A roughly square block (aspect ratio near 1.0) is the safe default because it minimises the worst-case Manhattan distance between any two points.

Long, thin blocks are sometimes forced by the top-level plan, but they carry real costs: cross-block paths become long, the clock tree has to travel further and gets deeper, and routing resources in the narrow dimension run out early. If a non-unity aspect ratio is unavoidable, the datapath should be oriented along the long axis so that the critical signals run with the shape rather than across it.

Macro placement

Hard macros — memories, PLLs, analog blocks, IP hardened elsewhere — are placed by hand or by a macro placer, and this is where most floorplan quality is won or lost. The working rules:

• Push macros to the edges and keep the centre of the block open for standard cells. Macros stranded in the middle split the core into regions that are awkward to route between.
• Orient pins inward. A memory whose pins face the die edge forces every connection to route around the macro body.
• Group macros that talk to each other. Connectivity-aware grouping shortens the buses that dominate wire length.
• Leave channels between macros wide enough for routing and for the buffers those long nets will need. Channels that are too narrow become congestion hot spots and, in the worst case, unroutable.
• Avoid notches and pockets — concave regions of standard-cell area trap the placer and create local congestion.

Halos, blockages and keep-outs

A halo (also called a keep-out margin) is a region around a macro where standard cells may not be placed. Without it, the placer will pack cells hard against the macro edge, leaving no room for the routing that must escape the macro’s pins, and no room for buffers on the nets entering it.

Placement blockages come in flavours worth distinguishing: hard blockages exclude all cells, soft blockages exclude the placer but allow optimisation to add buffers later, and partial blockages cap the local density to a chosen percentage. Partial blockages are the usual tool for relieving a congestion hot spot without giving up the area entirely.

Power planning

The power grid is built during floorplan, before any standard cell is placed, because it consumes routing resource that everything else must then work around. The structure is a ring around the core, straps across it on the upper metal layers, and rails that feed the standard cell rows.

The trade-off is direct: a denser grid lowers IR drop and improves electromigration margin, but it consumes metal tracks that signal routing then cannot use. Under-building the grid produces IR drop that degrades cell delay and can silently break timing signoff; over-building it produces congestion. Both failure modes are expensive to discover late, which is why early IR-drop analysis on the floorplan is worth the effort.

Pin and port placement

For a block within a hierarchical design, pin placement determines where signals enter and leave. Pins should be placed near the logic they serve and consistently with the neighbouring blocks at the top level, otherwise every crossing signal pays a detour. Randomly ordered or clustered pins create congestion right at the block boundary — the one place where there is no room to spread out.

How to tell a floorplan is working

• Congestion maps from a trial placement and global route show no persistent hot spots.
• Timing from trial placement is within reach — not closed, but not showing paths that are hundreds of picoseconds away.
• IR drop on the initial grid is within budget.
• No unroutable channels between macros.

The important discipline is to iterate the floorplan against these signals early. Floorplanning is cheap to redo at the start and ruinously expensive to redo after clock tree synthesis.

Frequently asked questions

What is the difference between floorplanning and placement?

Floorplanning fixes the block’s boundary, the macros, the power grid and the pins. Placement then positions the standard cells inside the space the floorplan left. Floorplanning is largely a human-guided architectural step; placement is an automated optimisation within its constraints.

What core utilisation should I start with?

Around 65–75% is a common starting point for a block with moderate macro content, then adjusted from what the first congestion and timing runs show. There is no universal number — a routing-limited design wants lower, an area-critical one pushes higher.

Why keep macros at the edge of the block?

Macros at the edge leave a single contiguous region for standard cells. Macros in the centre fragment that region, create channels that are hard to route, and force the clock tree to detour around obstacles it cannot cross.

Why This Matters for Placements

VLSI hiring teams consistently probe these core fundamentals during technical mock interview loops. At ChipXpert, our curriculum is systematically designed to match these expectations, ensuring every student has hands-on experience resolving these challenges in our labs.