PVT in VLSI stands for Process, Voltage, and Temperature — the three environmental variables that change how fast transistors switch. Chips are verified across PVT “corners” (worst-case combinations like slow-process/low-voltage/high-temperature) to guarantee they work in every unit shipped, in every environment.
The Three Variables Explained
- Process (P): manufacturing variation — no two transistors are identical. Wafers are classified slow (SS), typical (TT), or fast (FF).
- Voltage (V): supply voltage droops under load and varies with the regulator — typically ±10% around nominal. Lower voltage = slower switching.
- Temperature (T): from -40°C (automotive cold start) to 125°C (junction under load). Higher temperature usually slows transistors — though at low voltages temperature inversion can reverse this.
What Are PVT Corners?
A corner is one specific combination, written like ss_0.72v_125c. The classic worst cases: setup timing is checked at the slow corner (SS, low V, high T) because signals are slowest there; hold timing is checked at the fast corner (FF, high V, low T) because data races the clock. Modern signoff uses 8-20+ corners combined with RC extraction corners.
Why PVT Matters in Real Design Work
Every timing report you sign off in STA is per-corner. A chip that meets timing at TT but fails at SS will fail in the field for a fraction of manufactured units — a multi-million-dollar respin. This is why physical design engineers close timing across all corners simultaneously (MMMC), and why libraries ship characterized at each corner.
PVT in VLSI — FAQ
What is the worst-case PVT corner?
For setup/performance: slow process, minimum voltage, maximum temperature (e.g., ss_0.9v_125c). For hold: fast process, maximum voltage, minimum temperature. Both must pass.
What is temperature inversion?
At low supply voltages (near-threshold), transistors actually get FASTER at high temperature — the opposite of classical behavior. Modern low-voltage nodes must therefore also check the low-temperature slow corner.
How many PVT corners are used in signoff?
Advanced nodes typically sign off 8-20+ timing corners (process × voltage × temperature × RC extraction), managed together through multi-mode multi-corner (MMMC) analysis.
Learn corner-based timing closure on real Cadence and Synopsys tools in the ChipXpert Physical Design course.
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