What is HDL? Hardware Description Languages: Verilog, VHDL and SystemVerilog

HDL stands for Hardware Description Language: a language for describing the structure and behaviour of digital circuits. Unlike C or Python, which describe a sequence of instructions for a processor, an HDL describes hardware that exists all at once and runs in parallel. The two industry-standard HDLs are Verilog (with its extension SystemVerilog) and VHDL.

Why software languages do not describe hardware

In a program, one statement runs after another. In a circuit, every gate is active at the same time: a million flip-flops all update on the same clock edge, and signals propagate through wires concurrently. An HDL has to express concurrency, timing (clock edges, delays), bit-level widths and connectivity (which output drives which input). Software languages have none of these as first-class concepts.

What an HDL is used for

• Design: writing the RTL of an ASIC or FPGA.
• Simulation: running the design with a testbench to check behaviour before any silicon exists.
• Synthesis: an EDA tool reads the HDL and produces a gate-level netlist, the real circuit.
• Verification and modelling: testbenches, bus-functional models and reference models are also written in HDL (mostly SystemVerilog today).

Levels of abstraction

See what RTL means in VLSI for the level designers spend most of their time at.

Verilog vs VHDL vs SystemVerilog

The same counter in Verilog and VHDL

Verilog:

module counter #(parameter W = 8) (
  input              clk,
  input              rst_n,
  input              en,
  output reg [W-1:0] count
);
  always @(posedge clk or negedge rst_n)
    if (!rst_n)   count <= '0;
    else if (en)  count <= count + 1'b1;
endmodule

VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
  generic (W : integer := 8);
  port (clk, rst_n, en : in  std_logic;
        count          : out unsigned(W-1 downto 0));
end entity;

architecture rtl of counter is
  signal cnt : unsigned(W-1 downto 0);
begin
  process (clk, rst_n)
  begin
    if rst_n = '0' then
      cnt <= (others => '0');
    elsif rising_edge(clk) then
      if en = '1' then cnt <= cnt + 1; end if;
    end if;
  end process;
  count <= cnt;
end architecture;

Both describe identical hardware: a bank of flip-flops with an incrementer and an enable. The tool produces the same netlist from either.

Synthesizable vs non-synthesizable HDL

Only a subset of each language maps to hardware. Delays (#10), initial blocks (in ASIC flows), file I/O, $display and class-based code are for simulation only. Writing synthesizable RTL means thinking in terms of registers and combinational logic, avoiding unintended latches, and handling resets and clock domains correctly. These are the habits taught in the RTL design course.

Key HDL concepts that have no equivalent in software

• Concurrent statements. Every assign and every always block runs at the same time. Order in the file does not mean order in time.
• Clock edges. always @(posedge clk) describes flip-flops that all update together on the rising edge, which is how synchronous hardware works.
• Blocking vs non-blocking assignment. = (blocking) is used for combinational logic inside a procedural block; <= (non-blocking) is used for registers so that all flip-flops sample their inputs before any output changes. Mixing them up is the classic source of simulation-versus-synthesis mismatches.
• Bit widths and vectors. Every signal has a declared width; arithmetic truncates and extends according to rules the designer must know.
• Four-state logic. Signals can be 0, 1, X (unknown) or Z (high impedance). X at reset and Z on a tri-state bus are things software never deals with.
• Parameters and generate. Designs are parameterised by width or depth and unrolled at elaboration time, not at run time.
• Sensitivity lists and inferred latches. A combinational block that does not assign every output on every path creates a latch the designer did not intend.

How HDL fits into the design flow

1. Write RTL in Verilog, SystemVerilog or VHDL to describe the design.
2. Simulate it with a testbench, also written in HDL, to confirm the behaviour (see the Verilog testbench tutorial).
3. Lint and check for coding problems, clock-domain crossings and unsynthesizable constructs.
4. Synthesize the RTL into a gate-level netlist using a standard-cell library (ASIC) or device primitives (FPGA; see the FPGA design flow).
5. Verify equivalence between RTL and netlist, then run gate-level simulation with timing.
6. Implement the netlist physically; the HDL is no longer edited unless a bug forces a change.

The HDL is the master description for the entire project: documentation, verification, synthesis and silicon all trace back to it.

Common beginner mistakes in HDL

• Writing sequential-looking code and expecting it to execute in order.
• Using blocking assignments for registers, or non-blocking for combinational logic.
• Forgetting a default assignment and inferring a latch.
• Using delays (#10) in design code; they are ignored by synthesis.
• Driving one signal from two always blocks.
• Relying on initial values of registers without a reset.
• Ignoring synthesis warnings, which usually describe exactly these problems.

Which HDL should you learn?

For a VLSI career in India, start with Verilog, then move to SystemVerilog, because design teams use Verilog/SystemVerilog and verification teams use SystemVerilog with UVM. Learn VHDL if you target FPGA work in defence, aerospace or European companies. Read Verilog vs SystemVerilog for the details, and practise with the Verilog testbench tutorial.

Frequently asked questions

What does HDL stand for?

Hardware Description Language: a language used to describe digital circuits for simulation and synthesis.

Which are the two main HDLs?

Verilog (and its superset SystemVerilog) and VHDL. Both are IEEE standards and supported by every major EDA tool.

Is HDL a programming language?

It has programming-language syntax, but it describes concurrent hardware rather than sequential instructions. Treating it like software is the most common beginner mistake.

Can HDL code run on a processor?

No. HDL is simulated by a simulator or synthesized into a circuit. It does not execute like a program.

Is SystemVerilog an HDL or an HVL?

Both. Its design subset is an HDL; its class-based, constrained-random and assertion features make it a hardware verification language (HVL).