TCL Scripting for VLSI: Constraints, Flows and Design Queries

TCL (Tool Command Language) is the scripting language built into almost every EDA tool, which makes it a required skill for synthesis, static timing analysis, place-and-route and DFT engineers. Timing constraints are TCL. Flow scripts are TCL. The interactive shell you type into inside the tool is a TCL interpreter. Learning it well is the fastest productivity gain available to a VLSI engineer.

Why EDA tools use TCL

TCL was designed in the late 1980s to be embedded inside applications as a command language. EDA vendors adopted it because it let them expose every tool command as a TCL procedure, so users could script, loop and automate without the vendor writing a new language. Decades later it is the common denominator: switch tools or vendors and the TCL knowledge carries over, even though the command names change.

TCL basics every VLSI engineer needs

# variables and substitution
set top   "cpu_core"
set clk_p 2.0                     ;# ns
puts "Design $top, period ${clk_p} ns"

# arithmetic uses expr
set half [expr {$clk_p / 2.0}]

# lists
set corners {ss_0p72v_125c tt_0p80v_25c ff_0p88v_m40c}
foreach c $corners { puts "corner: $c" }
puts [llength $corners]
puts [lindex $corners 0]

# control flow
if {$clk_p < 1.0} { puts "fast clock" } else { puts "normal clock" }
for {set i 0} {$i < 4} {incr i} { puts "iteration $i" }

# procedures
proc report_header {name} {
    puts "===== $name ====="
}
report_header "Timing summary"

# string handling and regular expressions
set cell "AND2_X4"
if {[regexp {^(\w+)_X(\d+)$} $cell -> func drive]} {
    puts "function $func drive $drive"
}

Three rules explain most TCL confusion: everything is a string; square brackets run a command and substitute its result; braces prevent substitution (which is why expr and if conditions are braced).

TCL as the constraints language

Design constraints (SDC) are TCL commands understood by synthesis and timing tools:

create_clock -name clk -period 2.0 [get_ports clk]
create_generated_clock -name clk_div2 -source [get_ports clk] -divide_by 2 [get_pins u_div/q]
set_input_delay  -clock clk 0.6 [get_ports {data_in[*]}]
set_output_delay -clock clk 0.8 [get_ports {data_out[*]}]
set_false_path -from [get_ports rst_n]
set_multicycle_path 2 -setup -from [get_pins u_mul/*/CK] -to [get_pins u_acc/*/D]
set_max_delay 1.5 -from [get_clocks clk_a] -to [get_clocks clk_b]

Because constraints are TCL, you can generate them: loop over a list of interface ports and apply the same input delay, or compute periods from a frequency table. Our STA guide explains what each constraint means.

Driving the flow with TCL

A physical design flow is a sequence of tool commands, each of which is TCL. A simplified skeleton:

read_netlist   ${top}.v
read_sdc       ${top}.sdc
init_design
create_floorplan -core_utilization 0.65
place_opt_design
clock_opt_design
route_opt_design
report_timing -max_paths 20 > reports/timing_post_route.rpt
write_def      ${top}_routed.def

Wrapping these in procedures with arguments turns a one-off session into a repeatable flow that any team member can run, which is how production flows are built.

Querying the design database

The real power is interactive querying. Tools expose collections of design objects (ports, pins, cells, nets, clocks) and TCL lets you filter and act on them:

# all flip-flops in a hierarchy
set regs [get_cells -hier -filter "is_sequential == true" u_core/*]

# count cells by reference name
foreach_in_collection c [get_cells -hier *] {
    set ref [get_attribute $c ref_name]
    incr count($ref)
}
foreach r [lsort [array names count]] { puts "$r : $count($r)" }

# upsize every buffer driving a long net
foreach_in_collection n [get_nets -filter "wire_length > 500"] {
    set drv [get_pins -leaf -of_objects $n -filter "direction == out"]
    size_cell [get_cells -of_objects $drv] BUF_X8
}

The exact command names vary by tool; the TCL patterns (collections, filters, attributes, loops) are the same everywhere.

Parsing reports

TCL reads files and matches text with regexp, so a script can extract worst negative slack from a timing report, collect DRC counts across runs, or compare utilisation between two floorplans. For heavy data processing many teams hand the report to Python instead; see scripting vs programming languages for how the two divide the work.

Good habits

• Brace expressions: if {$a > $b}, never if $a > $b.
• Use catch around commands that may fail so a flow script reports the error instead of dying silently.
• Keep flow steps in procedures with explicit arguments; avoid global variables except for a small, documented set.
• Log every run: puts to a log file with timestamps and the tool version.
• Version-control your TCL alongside the RTL and constraints.

Learning path

1. Core TCL syntax: substitution, lists, control flow, procedures, regexp (two or three days of practice).
2. SDC constraints and what each one means in STA.
3. Your tool’s object model: how to get cells, pins and nets and read their attributes.
4. Build a small flow from netlist to routed design, then automate the reports.

All four steps are covered with hands-on tool access in our VLSI scripting course (Python, TCL, Perl), and TCL is used throughout the physical design course and the DFT course.

Frequently asked questions

What is TCL used for in VLSI?

Writing timing constraints (SDC), running and automating synthesis, STA, place-and-route and DFT flows, querying the design database, and parsing reports. It is the native command language of most EDA tools.

Is TCL hard to learn?

No. The syntax is small. The parts that take practice are substitution rules (brackets and braces) and each tool’s object model.

TCL or Python for VLSI?

Both. TCL is unavoidable inside the tools; Python is better for data processing, report analysis and anything outside the tool. Most engineers use TCL inside the tool and Python around it.

What is SDC?

industry-standard EDA tools Design Constraints format: a set of TCL commands (create_clock, set_input_delay, set_false_path and others) that describe the timing requirements of a design. It is read by synthesis, STA and place-and-route tools from every vendor.

Which VLSI roles need TCL?

Physical design, STA, synthesis, DFT and CAD/flow engineers use it daily. RTL and verification engineers use it less, mainly for simulator and waveform control.