What is a Netlist in VLSI? Types, Formats and Where It Is Used

A netlist is a description of a circuit as a list of components and the nets (wires) that connect them. In VLSI it is the hand-off between almost every stage: synthesis produces a gate-level netlist from RTL, place-and-route consumes and modifies it, and physical verification compares the layout against it. If RTL is the design’s intent, the netlist is the design’s structure.

What a netlist contains

• Instances: each component, with a unique instance name and a reference to its type (a standard cell such as NAND2_X1, a macro such as an SRAM, or a sub-module).
• Nets: named electrical connections.
• Connectivity: which instance pin connects to which net.
• Ports: the connections of the block to the outside.
• Hierarchy: modules that contain instances of other modules, unless the netlist has been flattened.

A netlist has no timing, no placement and no geometry on its own. Those come from library files, constraints and the layout database.

Types of netlist

Netlist formats

• Verilog netlist: structural Verilog using only module instantiations and wires. The standard for digital hand-off between synthesis, place-and-route and simulation.
• EDIF: an older vendor-neutral interchange format, still seen in FPGA and schematic tools.
• SPICE / CDL: transistor-level text formats for simulation and for the schematic side of LVS.
• DEF: not a netlist by itself, but carries the netlist’s connectivity together with placement and routing of a physical design.

A gate-level Verilog netlist example

The RTL expression assign y = (a & b) | c; might synthesize to:

module f (a, b, c, y);
  input  a, b, c;
  output y;
  wire   n1;

  AND2_X1 U1 (.A1(a), .A2(b), .ZN(n1));
  OR2_X1  U2 (.A1(n1), .A2(c), .ZN(y));
endmodule

Every instance names a library cell and connects its pins to nets; there is no behavioural code left. A real netlist for a block has millions of such lines.

Where netlists are created and changed in the flow

1. Synthesis reads RTL, constraints and the cell library and writes the first gate-level netlist. See RTL and the standard-cell library.
2. DFT insertion adds scan chains and test logic, producing a new netlist (see scan chain insertion).
3. Place-and-route adds buffers, clock tree cells, tie cells, fillers and spare cells, and may resize or restructure logic; the post-layout netlist is written at the end. See the flow from netlist to GDSII.
4. ECO edits the netlist directly to fix late bugs or timing; see ECO in physical design.
5. Layout extraction produces a transistor-level netlist from the drawn shapes for LVS and parasitic simulation.

Checks that rely on the netlist

• Logical equivalence checking proves that the post-synthesis or post-layout netlist implements the same function as the RTL.
• Gate-level simulation runs the testbench on the netlist, with SDF timing after layout, to catch X-propagation, reset and timing issues that RTL simulation cannot.
• LVS compares the extracted layout netlist with the schematic or source netlist, device by device and net by net.
• STA times the netlist using library delays and extracted parasitics.

Common netlist problems

• Floating inputs or multiply driven nets, usually from integration mistakes; caught by lint, ERC and synthesis warnings.
• Name mismatches between RTL, netlist and constraints after a tool renames hierarchy or escapes identifiers.
• Missing cells: a netlist referencing a cell not in the library version the next tool loads.
• Hierarchy mismatches between the netlist used for STA and the one used for simulation, after flattening or ungrouping.

Learn the flow

Reading and debugging netlists is a daily task in physical design, DFT and gate-level verification. Our beginner VLSI course introduces the design flow in which each netlist appears.

Frequently asked questions

What is a netlist in simple terms?

A list of all the components in a circuit and the wires that connect them. It describes structure, not behaviour or geometry.

What is the difference between RTL and a netlist?

RTL describes behaviour (what the logic does, clock by clock) in an HDL. A netlist is the structural result of synthesis: specific gates and their connections.

What is a gate-level netlist?

A netlist whose components are standard cells (gates, flip-flops) and macros from the target library, produced by synthesis and updated by place-and-route.

What is a SPICE netlist?

A transistor-level netlist in SPICE syntax, used for analog circuit simulation and for the schematic side of layout-versus-schematic checking.

Why does the netlist change after place-and-route?

The implementation tool adds clock tree buffers, repeaters, hold-fix buffers, tie cells, filler and spare cells, and resizes gates to meet timing, so the final netlist differs from the synthesis output.