Power Gating vs Clock Gating: Differences, Cells and When to Use Each

Clock gating cuts dynamic power by stopping the clock to logic that is idle; power gating cuts leakage power by switching off the supply to blocks that are not needed. Both are standard low-power techniques in every modern SoC, and they solve different problems. A chip that only clock-gates still leaks; a chip that only power-gates still wastes energy clocking idle flip-flops.

Where CMOS power goes

Dynamic power (αCV²f) is consumed when nodes switch. In a synchronous design the clock network and the flip-flops it drives switch every cycle whether or not useful work happens, so the clock can be 30 to 40 percent of the dynamic power. Static (leakage) power flows whenever a block is powered, even with the clock stopped, and at advanced nodes it is a large share of total power in idle states. See power dissipation in CMOS circuits.

Clock gating

A clock-gating cell (an integrated latch-plus-AND, called an ICG) sits between the clock and a group of flip-flops. When the enable is low, the clock to those flops is held steady: they keep their value and nothing downstream toggles. The latch inside the ICG prevents glitches by only letting the enable change while the clock is low.

• Granularity: from a handful of flops (fine-grained, inferred by synthesis from enable conditions in RTL) to whole blocks (coarse-grained, controlled by a power manager).
• Cost: an ICG per gated group and an enable signal that must meet timing with respect to the clock.
• Wake-up: immediate; the next cycle after the enable rises.
• Saves: dynamic power of the clock tree segment, the flops and the logic they would have driven.
• Does not save: leakage.

RTL coding matters: if (en) q <= d; lets the synthesis tool infer gating; a feedback mux (q <= en ? d : q) is what it replaces.

Power gating

A power-gated block has its supply (or ground) connected through large header (PMOS) or footer (NMOS) switch transistors. When the block is idle, the switches open and the block floats at near-zero voltage, so leakage drops by orders of magnitude. The technique needs additional cells and careful design:

• Power switches: distributed across the block; turned on in a daisy chain to limit in-rush current.
• Isolation cells: clamp the block’s outputs to a known value so the floating outputs do not corrupt the always-on logic. See isolation cells.
• Retention registers: keep critical state on an always-on supply so the block can resume without a full reset.
• Level shifters: where the block runs at a different voltage from its neighbours.
• Power management controller: sequences isolation, save, switch-off, switch-on, restore and release.
• Wake-up: microseconds, limited by in-rush control and state restoration.

Power intent (which domains exist, what is retained, how isolation works) is captured in UPF so that synthesis, implementation and verification tools all apply it; see UPF in VLSI.

Clock gating vs power gating

Using both together

A typical mobile SoC clock-gates everything at fine granularity all the time, and power-gates large blocks (a CPU cluster, GPU, modem) when the power manager predicts they will stay idle long enough to repay the wake-up cost. Dynamic voltage and frequency scaling (DVFS) sits between the two, lowering V and f when full performance is not needed. Multi-threshold cell selection reduces leakage in the always-on parts.

Verification and sign-off

• Power-aware simulation checks that isolation and retention behave correctly through every power state transition.
• Static low-power checks confirm every domain crossing has isolation or a level shifter.
• Timing must be closed with switch-cell IR drop included, and clock-gating enables must meet setup against the gated clock.
• Power analysis at the gate level measures the real saving against the activity profile.

Learn low-power design

Clock gating, UPF, power domains and multi-voltage implementation are covered in our ASIC physical design course and the RTL-side techniques in the RTL design course. Read low-power VLSI design for the wider toolbox.

Frequently asked questions

What is the difference between clock gating and power gating?

Clock gating stops the clock to idle logic and saves dynamic power while preserving state; power gating cuts the supply to a block and saves leakage, at the cost of lost state (unless retained) and a slower wake-up.

Which saves more power?

Clock gating saves more during active operation; power gating saves more during long idle periods, because leakage is all that remains once the clock is stopped.

What is an ICG cell?

An integrated clock-gating cell: a latch and an AND gate in one library cell that gates a clock without glitches.

Why are isolation cells needed for power gating?

When a block is switched off its outputs float. Isolation cells clamp them to a defined value so that the powered logic they drive does not see unknown or intermediate voltages.

What is UPF?

Unified Power Format: an IEEE standard for describing power intent (domains, switches, isolation, retention, level shifting) so that every tool in the flow applies the same rules.