Verilog and SystemVerilog code is run by a simulator, synthesized by a synthesis tool and checked by lint and formal tools. Which software you use depends on whether you are learning, working on an FPGA, or working on an ASIC in industry. This guide lists the main categories, the free options to start with, and what industry teams use.
What you need to run Verilog
- A text editor or IDE with Verilog syntax support and, ideally, linting.
- A simulator that compiles your design and testbench and executes them.
- A waveform viewer to inspect signals over time.
- A synthesis tool when you want to see the hardware your code produces, or target an FPGA.
Free and open-source tools
| Tool | Type | Notes |
|---|---|---|
| Icarus Verilog (iverilog) | Simulator | Verilog-2005 and part of SystemVerilog; easy to install; standard for learning. Produces VCD waveforms. |
| Verilator | Simulator (compiles to C++) | Very fast for synthesizable code; supports much of SystemVerilog; used by RISC-V projects and in industry for large designs. No # delays in the usual mode. |
| GTKWave / Surfer | Waveform viewers | Open VCD and FST files from the simulators above. |
| Yosys | Synthesis | Open-source synthesis to generic gates or FPGA primitives; with OpenROAD it forms a complete open ASIC flow. |
| Verible | Lint and formatting | SystemVerilog style checker and formatter. |
| cocotb | Python testbench framework | Write testbenches in Python driving any simulator; see cocotb and Python in DV. |
| EDA Playground | Browser-based | Run small examples in the browser with several simulators, including commercial ones with limits; nothing to install. |
For a beginner, Icarus Verilog plus GTKWave on Linux (or WSL on Windows) covers everything up to moderately sized designs.
FPGA vendor tools
Each FPGA vendor provides a free edition of its design suite with a simulator, synthesis, implementation and bitstream generation for its devices. These are the natural choice when you have an FPGA board, because you can run the design on hardware. See the FPGA design flow.
Industry-standard EDA tools
ASIC design teams use commercial simulators from the major EDA vendors, which support the full SystemVerilog and UVM standard, assertions, coverage, debug environments and very large designs, together with commercial synthesis, static timing, place-and-route and formal tools. Licences are expensive and are provided by employers and training institutes rather than bought by individuals. The commands and flows differ, but the language and methodology are the same, so skills learned on free tools transfer. Our courses give students access to industry-standard EDA tools in the browser; see industry-standard EDA tools.
Choosing the right tool
| Goal | Use |
|---|---|
| Learning Verilog syntax and simulation | Icarus Verilog + GTKWave, or EDA Playground |
| Fast simulation of large synthesizable designs | Verilator |
| SystemVerilog classes, constrained-random, UVM | Commercial simulator (or a free educational licence where available) |
| Running on an FPGA board | Vendor FPGA suite |
| Seeing synthesized gates from RTL | Yosys, or the FPGA suite’s synthesis |
| Python-driven testbenches | cocotb with any of the simulators |
A minimal workflow with free tools
# compile design and testbench
iverilog -g2012 -o sim.out alu.v tb_alu.v
# run the simulation
vvp sim.out
# open the waveform written by $dumpfile
gtkwave alu.vcdAdd -Wall for warnings. For lint, run verilator --lint-only alu.v, which catches width mismatches, unused signals and latches that a plain simulation will not.
Learn on the real tools
Free tools are enough to learn the language. For a career in design or verification you also need time on the commercial tools used in industry, which is why our RTL design course and design verification course include browser-based access to industry-standard EDA tools alongside the open-source ones.
Frequently asked questions
Which software is used to run Verilog code?
A Verilog simulator. Free options are Icarus Verilog and Verilator; FPGA vendors bundle simulators with their suites; ASIC companies use commercial simulators from the major EDA vendors.
Is there a free Verilog simulator?
Yes: Icarus Verilog and Verilator are free and open source, and EDA Playground runs small examples in a browser.
Can I run Verilog online?
Yes, on EDA Playground and similar sites, which is convenient for small exercises and sharing examples.
Does Verilog need special hardware?
No. Simulation runs on any PC. Hardware is only needed when you want to run the design on an FPGA.
Which tool should a beginner start with?
Icarus Verilog with GTKWave, then Verilator for lint and speed, then an FPGA suite when you have a board.
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