What is a Clock Domain Crossing (CDC) and how is it synchronized?
Clock Domain Crossing (CDC) occurs when a signal transitions from one clock domain to another. Single-bit signals are synchronized using multi-flip-flop synchronizers. Multi-bit buses require Gray coding, handshaking protocols, or asynchronous FIFOs to prevent data incoherence.
The CDC Challenge
In modern System-on-Chip (SoC) architectures, multiple asynchronous clock domains run concurrently. Directly sampling a signal launch in Clock Domain A using a clock from Domain B will inevitably lead to setup/hold violations and metastability failures.
CDC Synchronization Strategies
Different types of signals require distinct CDC synchronization architectures:
- Single-bit Control Signals: Synchronized using a standard 2-FF synchronizer chain.
- Fast-to-Slow Pulse Signals: Synchronized using a pulse synchronizer (toggle register in launch, followed by 2-FF and edge detection in capture).
- Multi-bit Data Buses: Individual bit synchronization fails due to skew, leading to data incoherence. These require Handshake interfaces, Gray-coded bus transfers, or Asynchronous FIFOs.
Gray Coding in CDC
When crossing count indices (like FIFO pointers) across asynchronous boundaries, indices are converted to Gray Code. Since Gray Code only changes by a single bit per transition, it guarantees that capture registers never sample intermediate, erroneous values.
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