Cracking a DFT interview in 2026? Design for Test is one of the highest-demand, lowest-competition VLSI specializations. These are the DFT interview questions asked most often — scan, ATPG, MBIST and boundary scan — with answers that show interviewers you understand the why, not just the what.
Basic DFT Interview Questions
1. What is DFT and why is it needed?
Design for Test (DFT) adds testability structures to a chip so manufacturing defects can be detected efficiently. Without DFT, testing complex chips would be impractically slow and expensive; with it, testers achieve high fault coverage in seconds.
2. What is scan insertion?
Scan insertion replaces regular flip-flops with scan flops connected into shift-register chains. In test mode, patterns shift in through scan-in, the circuit captures a functional cycle, and results shift out for comparison — making internal state controllable and observable.
3. What are the common fault models?
Stuck-at (node permanently 0/1), transition delay (slow-to-rise/fall), path delay, bridging, and cell-aware faults. Stuck-at and transition are the workhorses of production test.
4. What is ATPG?
Automatic Test Pattern Generation algorithmically creates the minimal pattern set that detects modeled faults. Tools like Siemens Tessent and Synopsys TetraMAX report fault coverage — typically 98%+ stuck-at coverage is expected.
Intermediate Questions
5. What is scan compression and why is it used?
Compression (e.g., EDT) inserts a decompressor/compactor around scan chains so testers drive many internal chains through few pins — cutting test time and data volume 10–100x.
6. What is MBIST?
Memory Built-In Self-Test embeds controllers that test embedded memories at-speed with algorithms like March tests, since memories cannot be efficiently tested through scan.
7. What is boundary scan (JTAG)?
IEEE 1149.1 places scan cells at chip I/Os, letting board-level connections be tested through a 4/5-pin TAP interface — essential for board manufacturing test and debug access.
8. What are testpoints and why insert them?
Control and observe points added at hard-to-test nodes to improve coverage and reduce pattern count, typically guided by testability analysis.
Advanced Questions
9. What DFT challenges appear at advanced nodes?
Higher defectivity requires cell-aware and slack-based testing; low-power design needs power-aware ATPG so test power stays within limits; 3D-IC stacks need die-to-die test access (IEEE 1838).
10. Walk through your scan chain debug flow.
Verify scan enable and clocks, run chain integrity patterns, bisect failing chains via diagnosis, check lockup latches at domain crossings, and correlate silicon failures with simulation using diagnosis-driven layout analysis.
DFT Career Snapshot (India, 2026)
- DFT engineer salary: ₹5–20 LPA
- Demand consistently exceeds supply — fewer engineers specialize in DFT than PD or DV
- Core tools: Siemens Tessent, Synopsys DFTMAX/TetraMAX
Build these skills hands-on in the ChipXpert DFT Course with real Tessent flows, or start with the role of DFT in the chip life cycle. Freshers can apply for VLSI internships with placement support.
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