Free VLSI Mini-Course — 7-Day Walkthrough by ChipXpert

DAY 1 — INTRODUCTION

VLSI (Very Large Scale Integration) is the design of integrated circuits with millions to billions of transistors. Every smartphone, laptop, car, satellite, and AI accelerator runs on a VLSI chip.

The Indian semiconductor industry is in a rare moment: the Indian Semiconductor Mission (ISM), the Tata-PSMC Dholera fab, and Micron’s Sanand facility have created an unprecedented demand for VLSI engineers. Industry estimates 75,000+ open VLSI roles by 2027 in India alone.

The VLSI Design Flow (the map you need)

You don’t need to master all 8 stages. Pick ONE specialty (RTL, Verification, PD, DFT, Analog Layout, or FPGA) — go deep.

DAY 2 — RTL

Most courses teach Verilog as language syntax. Product companies care about something different.

What product companies actually look for:

1. Clock-domain awareness. Every signal carries an implicit clock-domain label. Crossing them without synchronisation is the #1 bug in fresher RTL.
2. Reset strategy. Synchronous vs asynchronous reset, distinguishing functional reset from power-on reset.
3. Bus protocol fluency. AMBA AXI master/slave handshake without looking it up. AHB and APB by reflex.
4. Synthesisable code style. always_ff for sequential, always_comb for combinational, no inferred latches.
5. Testbench reflex. Every RTL block comes with a basic SV testbench — not just a top-level file.

Recommended path:

• Master Verilog → SystemVerilog data types → SV interfaces and clocking blocks
• Build 3 small RTL projects: UART, SPI master, async FIFO
• Simulate every project in VCS or open-source Verilator
• Push code to GitHub — recruiters check

DAY 3 — VERIFICATION

If you’re targeting a verification role (and you should — they pay 10-20% more than RTL):

1. UVM is a methodology written in SystemVerilog. Master SV first (4-6 weeks of focused study).
2. Layered agents. Driver + monitor + sequencer pattern. Drill until muscle memory.
3. Sequences > tests. Reusable sequence libraries are what differentiates seniors from juniors.
4. Functional coverage is half the job. Writing covergroups + analysing coverage holes + driving constrained random to close gaps.
5. Real testbenches use uvm_reg / RAL. Most learners skip this and pay for it in interviews.

Common interview questions:

• “Explain the UVM phases — build, connect, run, extract, check, report.”
• “What is the factory pattern in UVM and why does it matter?”
• “Difference between blocking and non-blocking TLM calls?”
• “How do you implement end-of-test detection in UVM?”

DAY 4 — PHYSICAL DESIGN

The PD flow boiled down:

Floorplan → Power Plan → Placement → CTS → Routing → Signoff

Gotchas at each step:

See the full PD course:

→ Advanced Physical Design Course

DAY 5 — DFT

DFT (Design for Testability) is the most under-taught VLSI specialty and one of the best-paying.

3 things to learn:

1. Scan insertion — converts every flop into a shift register so you can drive test patterns and observe outputs.
2. ATPG (Tessent or TestMAX) — generates test patterns to detect stuck-at and transition faults.
3. MBIST — built-in self-test for memories. Every modern chip has hundreds of memories.

Why DFT pays:

• Demand outstrips supply 4:1 in India
• Tessent is industry standard — learning it makes you immediately employable
• Less competition from large institute graduates (most teach RTL/Verification heavily)

DAY 6 — INTERVIEW PREP

Memorise + practice these 7 questions:

1. “Explain setup and hold time.” Don’t memorise — draw the timing diagram. Show the relationship to clock period and combinational delay.
2. “What is metastability and how do you prevent it?” Answer: 2-flop synchroniser, Gray-code FIFOs.
3. “Difference between blocking and non-blocking assignments?” Show the simulation race condition with code.
4. “How do you design an async FIFO?” Gray-code pointers, 2-flop synchroniser per pointer.
5. “Explain UVM phases.” Bottom-up build, top-down connect, run is parallel.
6. “How do you close timing on a 5nm design?” Useful skew, ECO routing, swap-cells, downsize/upsize loops.
7. “Difference between scan and ATPG?” Scan is the DFT insertion; ATPG is the pattern generation.

Salary expectations by role:

→ VLSI Salary India 2026 — Full Breakdown

DAY 7 — CAREER ROADMAP

Career mistakes to avoid:

• Staying in services > 2 years (kills product-company moves)
• Switching specialties every 2 years (no depth)
• Not contributing to open source or publications (no external signal for promotions)
• Skipping interview practice between job changes (no leverage at appraisal)

The single biggest lever:

Switch companies every 3-4 years in the first decade. Internal promotions average 8-12% raises; external moves average 25-40%. Math doesn’t lie.

→ Join our next batch (starts 24th June 2026)