SystemVerilog interview questions come from seven areas: data types, procedural blocks, interfaces and scheduling, OOP, constrained randomisation, threads, and assertions and coverage. This page answers the questions that come up most often for design verification and RTL roles in India. Each answer is short enough to say aloud in an interview and explains the reasoning the interviewer is testing for.
For UVM-specific questions (factory, sequences, config_db, phases), see UVM interview questions. For the language comparison, see Verilog vs SystemVerilog.
Contents
- Basics and data types
- Procedural blocks and assignments
- Interfaces, clocking blocks and scheduling
- OOP for verification
- Randomisation and constraints
- Threads and inter-process communication
- Assertions and coverage
Basics and data types
1. What is the difference between logic, wire and reg?
wire is a net: it models a connection and needs a continuous driver, and multiple drivers are resolved. reg in Verilog is a variable assigned inside procedural blocks. SystemVerilog’s logic is a 4-state data type that can be driven either by one continuous assignment or procedurally, which removes most of the reg/wire confusion. The rule interviewers look for: use logic by default, and use a net type (wire/tri) only where a signal genuinely has multiple drivers, such as a bidirectional bus.
2. What is the difference between 2-state and 4-state types?
4-state types (logic, reg, integer, wire) hold 0, 1, X and Z. 2-state types (bit, byte, shortint, int, longint) hold only 0 and 1, use less memory and simulate faster. Use 2-state types in testbench code for counters and loop variables, but keep 4-state types on DUT interfaces: an X converted to 0 in a 2-state variable hides exactly the bugs (uninitialised flops, bus contention) that you want the simulation to expose.
3. Explain fixed-size, dynamic and associative arrays and queues.
A fixed-size array has its size set at compile time. A dynamic array (int d[];) is sized at run time with new[n]. An associative array (int a[string];) stores sparse entries indexed by any key type, which suits memory models with huge address spaces. A queue (int q[$];) grows and shrinks at either end with push_back, pop_front and so on, and is the natural structure for scoreboards that match expected against actual transactions.
4. What is the difference between packed and unpacked arrays?
Packed dimensions come before the name (logic [7:0] data;) and are stored as one contiguous vector that can be sliced and used in arithmetic. Unpacked dimensions come after the name (logic data [8];) and form a collection of separate elements. logic [3:0][7:0] mem [16]; is 16 unpacked elements, each a 32-bit packed vector made of four bytes.
5. What are struct, union and typedef enum used for?
typedef struct packed groups related fields, such as a packet header, into one vector that can still be assigned as a whole. A union gives several views of the same storage. typedef enum logic [1:0] {IDLE, BUSY, DONE} state_t; gives FSM states readable names, lets simulators show state names in waveforms, and catches illegal assignments at compile time.
Procedural blocks and assignments
6. What is the difference between always_comb, always_ff and always_latch?
They state design intent, so tools can check it. always_comb infers its sensitivity list automatically, runs once at time zero, and makes lint and synthesis tools warn if the logic would infer a latch. always_ff @(posedge clk) must describe flip-flops, and tools flag combinational or blocking-assignment misuse. always_latch documents a deliberate latch. A plain always block states none of this intent.
7. Blocking vs non-blocking assignments: when do you use each?
Blocking (=) updates immediately, in order. Non-blocking (<=) schedules the update for the end of the time step, so every right-hand side is sampled before any left-hand side changes. Use <= in sequential logic (always_ff) and = in combinational logic (always_comb). Mixing them in the same flop block causes simulation–synthesis mismatches and race conditions, and it is one of the most frequently asked follow-ups.
8. What do unique and priority do on a case or if?
unique case asserts that exactly one branch matches, so the simulator warns on overlaps or no match, and synthesis may build parallel logic. priority case asserts at least one branch matches, and the first match wins. Both replace the old full_case/parallel_case synthesis pragmas, which changed synthesis results without changing simulation behaviour.
Interfaces, clocking blocks and scheduling
9. Why use an interface and a modport?
An interface bundles a protocol’s signals so they are declared once and passed as one port instead of dozens. Modports define directions from each side’s view (for example, master, slave, monitor). In a UVM testbench the interface is how class-based components reach the DUT, through a virtual interface handle stored in uvm_config_db.
10. What problem does a clocking block solve?
A clocking block defines when the testbench samples inputs and drives outputs relative to a clock edge, using input and output skews. This removes races between the testbench and the DUT: sampling happens in the Preponed region, before the edge’s updates, and driving happens after the edge. The result is testbench behaviour that doesn’t depend on the order in which the simulator happens to run processes.
11. What is the purpose of the program block?
Program block code runs in the Reactive region, after the design’s events for that time step have settled, which avoids testbench–design races. Most modern UVM testbenches use modules plus clocking blocks instead, but it is still asked about to check your understanding of the scheduler.
12. Name the main SystemVerilog scheduling regions.
In order within a time step: Preponed (sampling for assertions and clocking blocks), Active (blocking assignments and continuous assignments), Inactive (#0), NBA (non-blocking assignment updates), Observed (assertion evaluation), Reactive (program block code and assertion action blocks), and Postponed ($strobe, $monitor). You don’t need to recite every region; being able to explain why non-blocking assignments and clocking blocks prevent races is what counts.
OOP for verification
13. What is the difference between a class and a module?
A module is static hardware: it is instantiated once at elaboration and exists for the whole simulation. A class is a dynamic software object: it is created with new() at run time, can be created and destroyed repeatedly, supports inheritance and polymorphism, and cannot contain always blocks or be instantiated as hardware. Transactions, drivers and scoreboards are classes; the DUT and the interfaces are modules.
14. Explain virtual methods and polymorphism with an example.
Declaring virtual function void display(); in a base transaction class lets a derived class override it. A base-class handle that points to a derived object then calls the derived version at run time. This is what lets a UVM test replace a sequence item or driver with an extended one, through the factory, without editing the environment code.
15. What is a shallow copy vs a deep copy?
b = new a; makes a shallow copy: the object’s own properties are copied, but any handles inside it still point to the same nested objects. A deep copy also creates new copies of the nested objects, usually through a user-written copy() method (in UVM, do_copy). Scoreboards need deep copies, otherwise a later modification by the monitor silently changes transactions that are already stored.
16. What are static, local and protected members?
A static property is shared by all objects of the class; a static transaction ID counter is the classic example. local members are visible only inside that class. protected members are visible inside the class and its subclasses. Interviewers use this question to test encapsulation, not memorisation.
17. What is a parameterised class, and what is the extern keyword for?
class fifo #(type T = int, int DEPTH = 8); makes one reusable definition that works for any item type or size; UVM’s uvm_tlm_fifo #(T) is built this way. extern declares a method prototype inside the class and defines its body outside with classname::method, which keeps long class definitions readable.
Randomisation and constraints
18. What is the difference between rand and randc?
rand variables take uniformly distributed values that can repeat. randc variables are random-cyclic: they go through every possible value once before any value repeats, which is useful for small spaces such as opcodes. randc is expensive on wide variables, so keep it to a few bits.
19. How do dist, inside, solve…before and soft constraints work?
inside {[0:15], 32} restricts a value to a set or range. dist {0 := 40, [1:9] :/ 60} weights the distribution: := gives the weight to each value, and :/ divides the weight across the range. solve mode before length; changes the probability distribution, not which solutions are legal. A soft constraint is a default that a test can override with an inline randomize() with {...} constraint without causing a conflict.
20. What are pre_randomize and post_randomize used for?
They are callbacks that run automatically around randomize(). pre_randomize can set up state or switch constraints on and off. post_randomize computes values derived from the random fields, such as a CRC or parity over the randomised payload.
21. How do you turn constraints or random variables off at run time?
obj.c_name.constraint_mode(0) disables a constraint block, and obj.field.rand_mode(0) fixes a variable so it keeps its current value. Always check the return value of randomize(). A failed randomisation leaves old values in place, and the test keeps running on stale stimulus without any visible error.
Threads and inter-process communication
22. Explain fork…join, join_any and join_none.
join waits for every thread to finish. join_any continues when the first thread finishes, and is often used for a timeout race. join_none starts the threads and continues immediately. After join_any or join_none, use disable fork or wait fork deliberately so no stray threads are left running.
23. Mailbox vs semaphore vs event: when do you use each?
A mailbox passes transactions between processes, such as a generator to a driver; it can be bounded, and get blocks when it is empty. A semaphore gives mutually exclusive access to a shared resource, such as one bus driven by two sequences. An event is a pure synchronisation signal. Use wait(ev.triggered) rather than @ev when the trigger could happen in the same time step as the wait begins, or the wait can miss it.
Assertions and coverage
24. What is the difference between immediate and concurrent assertions?
An immediate assertion (assert (a == b);) is evaluated like an if-statement at the point where it executes in procedural code. A concurrent assertion (assert property (@(posedge clk) req |-> ##[1:3] ack);) is evaluated on a clock across time, using values sampled in the Preponed region, and can describe multi-cycle protocol behaviour. Formal verification tools use concurrent assertions.
25. Explain |-> vs |=>, and $rose, $past and disable iff.
With a |-> b (overlapping implication), b is checked in the same cycle that a matches. With a |=> b (non-overlapping), b is checked one cycle later, which is equivalent to a |-> ##1 b. $rose(sig) detects a 0-to-1 change between samples, and $past(sig, n) gives the value from n cycles earlier. disable iff (!rst_n) stops the property from being evaluated during reset, so resets don’t produce false failures.
26. What is the difference between code coverage and functional coverage?
Code coverage (line, branch, condition, toggle, FSM) is collected automatically and shows which parts of the RTL were exercised. Functional coverage is written by you, with covergroup, coverpoint, bins and cross, and shows which features from the verification plan were exercised. You can have 100% code coverage with a missing feature, because code coverage cannot tell you about logic that was never written. Sign-off needs both.
27. What are illegal_bins, ignore_bins and cross coverage?
ignore_bins excludes values that don’t matter from the coverage calculation. illegal_bins raises an error if a value that should never occur is sampled. cross addr_cp, rw_cp; measures combinations, for example that every address range was both read and written. Unrestricted crosses grow quickly, so restrict them with binsof and intersect.
How to prepare for a SystemVerilog interview
- Write code, not notes. Build a small testbench for a FIFO: a transaction class, constrained random stimulus, a mailbox-based driver, a monitor, a queue-based scoreboard, one covergroup and three assertions. Almost every question above appears in that one exercise.
- Be ready for “why”. Interviewers follow up on answers about races, shallow copies and failed
randomize()calls with “what bug would that cause?” - Tie answers to your project. “I used
randcfor opcodes so every command was hit early” is stronger than a textbook definition. - Practise on a real simulator. Watch scheduling and X-propagation behave in a waveform; don’t rely on memorised descriptions.
Frequently asked questions
What are the most common SystemVerilog interview questions?
The most common are logic vs wire vs reg, blocking vs non-blocking assignments, always_comb vs always_ff, clocking blocks and race conditions, shallow vs deep copy, virtual methods and polymorphism, rand vs randc, fork-join variants, mailbox vs semaphore, immediate vs concurrent assertions, and code vs functional coverage.
Is SystemVerilog enough for a verification job, or do I also need UVM?
For most design verification roles in India you need both. SystemVerilog is the language, and UVM is the methodology built on its classes. Interviews usually start with SystemVerilog fundamentals and then move to UVM components, sequences and the factory.
How long does it take to prepare for a SystemVerilog interview?
With a solid digital-design base, most engineers need several weeks of hands-on practice: writing a complete class-based testbench, randomisation and coverage. Reading answers alone is rarely enough, because interviewers ask follow-up questions about bugs you would actually hit.
