DFT syllabus: design for testability, scan, ATPG and MBIST
Syllabus view of the DFT training: fault models, scan, ATPG, compression, MBIST and boundary scan, module by module.
This page lists what the DFT (Design for Testability) training covers. To join a batch, see the Design for Test course or the DFT online course. See the Design for Test (DFT) course.
Testing fundamentals
Manufacturing defects, fault models (stuck-at, transition) and test coverage.
Scan design
Scan flip-flops, scan chains, scan styles and design rules.
Scan insertion flow
Inserting and stitching scan chains, handling clocks, resets and lock-up latches.
ATPG
Pattern generation, coverage analysis and debugging untested faults.
Test compression
Why compression is needed and how compressed patterns reduce test time.
Memory BIST (MBIST)
Memory test algorithms and BIST controller integration.
Boundary scan
JTAG and IEEE 1149.1 test access.
DFT signoff
Pattern simulation, coverage targets and handoff.
Who should join
B.E / B.Tech, M.E / M.Tech and M.Sc students and graduates in ECE, EEE and related branches, and working engineers moving into VLSI.
Roles this prepares you for
- DFT Engineer
- ATPG Engineer
- Test Engineer
ChipXpert provides placement assistance: resume building, mock interviews and interview preparation. It is assistance with your job search, not a guarantee of employment.
Formats and locations
Live online with recorded sessions, or classroom at our Hyderabad (Madhapur) and Bengaluru (Bellandur) centres, with 24x7 access to industry-standard EDA tools in your browser. Explore the DFT hub and the batch calendar.
Frequently asked questions
What is DFT training?
It teaches how to add test structures such as scan and BIST to a chip so manufacturing defects can be detected efficiently.
Is the DFT course online?
Yes, live online with recorded sessions, or classroom at our Hyderabad and Bengaluru centres.
Skills you will gain
- Scan
- ATPG
- MBIST
- Boundary scan
- Coverage
Project work
Project work is modelled on industry practice. Typical project themes:
- A scan and ATPG flow with coverage report
Interview topics you will be ready for
- What is scan stitching?
- Fault models in DFT
- What is test compression?
- What is LBIST?
Learning path
Start with digital electronics fundamentals, learn the domain through the syllabus above, build project work, then prepare for interviews with mock rounds and resume reviews. Our beginner VLSI course is the starting point if you are new to VLSI.
Where we train
Hyderabad: our centre is in Madhapur, close to Hyderabad, Madhapur, HITEC City, Gachibowli, Kondapur, Kukatpally, Ameerpet, Secunderabad. Bengaluru: our centre is in Bellandur, close to Bengaluru, Bellandur, Marathahalli, HSR Layout, Koramangala, Sarjapur Road, Whitefield, Electronic City. Live online batches run across India and overseas.
More questions answered
What are the fees?
Programme fees run from ₹45,000 to ₹90,000 + applicable taxes depending on the format. See the fee page for the full table. EMI options over 3 to 6 months are available.
Is there a discount?
Yes, a merit-based discount of 50–60% (up to 60%) for eligible B.Tech/B.E, M.Tech/M.E and M.Sc students, assessed through a short aptitude interaction.
Is there a free demo class?
Yes. The demo class is free; share your details and a counsellor will arrange it.
Do you provide a course certificate and placement help?
Yes, a course certificate and placement assistance: resume building, mock interviews and interview preparation. Placement assistance is support for your job search, not a guarantee of employment.
When does the next batch start?
The next batch starts on 28th October 2026. A new batch begins every 21 days. See the course calendar.
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