Temperature Inversion in VLSI: Why Chips Get Faster When Hot at Low Voltage

Temperature inversion is the effect, seen at low supply voltages, where a CMOS circuit gets faster as the temperature rises, instead of slower. It overturns the traditional rule that the slowest corner is the hottest one, and it changes which process-voltage-temperature corners must be used for timing sign-off at advanced nodes.

Two competing effects of temperature

Transistor drive current depends on two temperature-sensitive quantities:

• Carrier mobility falls as temperature rises (more lattice scattering). Lower mobility means lower current and slower switching. This is the classic behaviour: hot is slow.
• Threshold voltage also falls as temperature rises. A lower threshold means more gate overdrive (V_GS − V_TH), which increases current and speeds switching.

Which effect wins depends on how much overdrive the transistor has. At a high supply voltage, V_GS − V_TH is large, a small drop in V_TH changes it little, and the mobility loss dominates: hot is slow. At a low supply voltage, the overdrive is small, so the same drop in V_TH is a large relative gain in current and it outweighs the mobility loss: hot is fast. The supply voltage at which the two effects cancel is the zero-temperature-coefficient (ZTC) point. Below it, delay has an inverted temperature dependence.

Why it matters now

Older processes ran at 1.8 V or 1.2 V, well above the ZTC point, so timing was always worst at high temperature and nobody needed the term. At 28 nm and below, nominal supplies are around 0.8 V and low-power modes go lower still, close to or below ZTC. In those designs the slowest operating point may be the cold corner, and signing off only at high temperature would miss real setup violations.

Effect on timing sign-off corners

Traditional worst-case setup corner: slow process, low voltage, high temperature (SS / V_min / 125 °C). With temperature inversion, a slow-process, low-voltage, low-temperature corner (SS / V_min / −40 °C) can be slower still. Sign-off therefore includes both:

Foundries characterise libraries at the extra temperatures, and the sign-off methodology document for a node lists which corners are mandatory. The PVT guide explains how corners are built, and the STA guide covers multi-corner analysis.

Not all cells invert the same way

The ZTC point depends on threshold voltage, so cell types behave differently:

• High-V_TH (HVT) cells have the least overdrive and invert at the highest supply; they are the most affected.
• Low-V_TH (LVT) cells have more overdrive and may still get slower when hot at the same supply.
• Interconnect delay always increases with temperature because metal resistance rises.

A path mixing HVT and LVT cells and long wires can therefore have a worst temperature that is neither extreme, which is one reason tools support analysis at intermediate temperatures and on-chip variation models (OCV) at each corner.

Implications for design

• Timing closure must consider both cold and hot slow corners; a design optimised only for the hot corner can fail cold.
• Hold fixes made at the classic cold-fast corner may be insufficient at the hot-fast corner.
• Low-power modes that drop VDD near threshold are the most affected; near-threshold and sub-threshold designs are always in the inverted region.
• Clock trees mixing cell types need balancing across temperatures, not just at one.
• Silicon characterisation (ring oscillators across temperature) should confirm the library’s ZTC behaviour.

Learn multi-corner timing closure

Choosing corners, running multi-corner multi-mode analysis and closing timing across them is a core part of our ASIC physical design course. For the device physics behind it, start with threshold voltage and the CMOS inverter.

Frequently asked questions

What is temperature inversion in VLSI?

The effect, at low supply voltage, where circuit delay decreases as temperature increases, because the threshold-voltage drop outweighs the mobility loss.

At what voltage does temperature inversion occur?

Below the zero-temperature-coefficient point, which depends on the process and the cell’s threshold voltage. For many modern nodes it is around or just below the nominal supply, so low-voltage modes are affected.

Which corner is the worst case for setup with temperature inversion?

Often slow process, minimum voltage and low temperature, in addition to the classic high-temperature corner. Both must be analysed.

Does temperature inversion affect hold timing?

Yes. The fastest corner may now be fast process, maximum voltage and high temperature, so hold must be checked there too.

Why did older designs not see temperature inversion?

Their supply voltages were far above the ZTC point, so the mobility effect always dominated and hot was always slow.