CMOS Inverter Explained: Working, VTC, Delay, Power and Applications

A CMOS inverter is a NOT gate built from one PMOS and one NMOS transistor. It outputs a logic 1 when its input is 0 and a logic 0 when its input is 1. It is the simplest CMOS logic gate and the starting point for understanding every other gate, standard cell and timing concept in VLSI.

Structure of the CMOS inverter

The PMOS transistor sits between the supply (VDD) and the output; the NMOS sits between the output and ground (VSS). Both gates are tied to the input, and both drains are tied to the output. “Complementary” refers to the pair: when one transistor is on, the other is off.

• Input = 0 (low): the PMOS turns on and pulls the output up to VDD; the NMOS is off. Output = 1.
• Input = 1 (high): the NMOS turns on and pulls the output down to ground; the PMOS is off. Output = 0.

Because there is never a direct path from VDD to ground in a steady state, the inverter draws almost no static current. This is the reason CMOS replaced earlier logic families and still dominates chip design.

Voltage transfer characteristic (VTC)

Plotting output voltage against input voltage gives the VTC. It has five regions as the input sweeps from 0 to VDD: PMOS linear / NMOS off, PMOS linear / NMOS saturated, both saturated (the steep transition), PMOS saturated / NMOS linear, and PMOS off / NMOS linear. The input voltage at which V_out = V_in is the switching threshold V_M. The VTC gives V_OH, V_OL, V_IH and V_IL, from which the noise margins are calculated. A sharp, symmetrical VTC is what makes CMOS logic robust.

Switching threshold and transistor sizing

Electrons move faster than holes, so an NMOS is stronger than a PMOS of the same size. To centre V_M at VDD/2, the PMOS is made roughly two to three times wider than the NMOS (the exact ratio depends on the process). Changing the width ratio shifts V_M, which is used deliberately in some circuits (for example Schmitt triggers and level restorers). The threshold voltages of the two devices also set where each turns on.

Propagation delay

The output does not switch instantly because the output node has capacitance (the next gate’s input, wiring and the inverter’s own drain). The high-to-low delay t_pHL depends on how fast the NMOS can discharge that capacitance; the low-to-high delay t_pLH depends on the PMOS. Propagation delay is reduced by wider transistors (more current), lower load capacitance, higher supply voltage and shorter channel length. Wider transistors, however, present more capacitance to the gate driving them, which is why logical effort and sizing are a design discipline of their own.

Power dissipation

• Dynamic (switching) power: P = α C V_DD² f. Every time the output switches, the load capacitance is charged from VDD or discharged to ground. This is the dominant term in active logic, and the V² dependence is why supply voltages have fallen with every process generation.
• Short-circuit power: during the input transition both transistors conduct for a moment, so a brief current flows from VDD to ground. Faster input edges reduce it.
• Static (leakage) power: sub-threshold and gate leakage even when nothing switches. Small per transistor, but significant across billions of them, which is why power gating and high-threshold cells exist.

See power dissipation in CMOS circuits for the full treatment.

Why the inverter matters in VLSI

Every CMOS gate is an extension of the inverter: a NAND adds NMOS devices in series and PMOS in parallel; a NOR does the opposite. Standard-cell libraries characterise their inverters at several drive strengths, and the inverter’s delay versus load is the basic unit used in timing models. Clock trees are built from inverters and buffers; ring oscillators made of inverters measure process speed on every wafer.

Applications of CMOS inverters

1. Logic NOT function in every digital block.
2. Buffers: two inverters in series drive large loads and long wires.
3. Clock tree buffering for distributing a clock with controlled skew.
4. Level restoration after pass-transistor logic, which degrades one logic level.
5. Delay elements in timing circuits and hold-fixing.
6. Ring oscillators for process monitoring, PLLs and true random number generators.
7. Schmitt triggers (with feedback) for noisy or slow inputs.
8. Sense amplifiers and SRAM cells: the 6T SRAM cell is two cross-coupled inverters.
9. Level shifters between voltage domains.
10. Analog use: biased in its transition region, an inverter works as a high-gain amplifier.

Learn CMOS design hands-on

Drawing the inverter, running its VTC and measuring its delay on a simulator is a first-week exercise in our analog circuit design course, and laying it out to design rules is the first exercise in the analog layout design course. Start with the stick diagram guide if you are new to layout.

Frequently asked questions

Why is it called a complementary MOS inverter?

Because it pairs a PMOS and an NMOS transistor that are complementary: for any steady input, exactly one of them conducts, so the output is driven firmly to VDD or ground with no static current path.

What is the switching threshold of a CMOS inverter?

The input voltage at which the output equals the input, usually designed to be about VDD/2 by sizing the PMOS wider than the NMOS.

Why is the PMOS wider than the NMOS?

Hole mobility is lower than electron mobility, so a PMOS needs more width to supply the same current as an NMOS and keep rise and fall delays balanced.

Does a CMOS inverter consume power when idle?

Only leakage power. Significant power is drawn only while the output switches (dynamic power) and briefly during the transition (short-circuit power).

How is a NAND gate related to an inverter?

A two-input NAND is an inverter with a second NMOS in series on the pull-down and a second PMOS in parallel on the pull-up.