Propagation Delay in VLSI: Definition, Formula & How to Reduce It

Propagation delay is the time a logic gate takes to change its output after its input changes — measured from 50% of the input transition to 50% of the output transition. It is the fundamental unit of timing in VLSI: every clock period budget is a sum of propagation delays.

Definition and How It’s Measured

• t_pHL — delay when output falls (high → low)
• t_pLH — delay when output rises (low → high)
• t_pd = (t_pHL + t_pLH) / 2 — average propagation delay

What Affects Propagation Delay in CMOS?

• Load capacitance (C_L) — more fanout/wire = slower
• Supply voltage (V_DD) — lower voltage = slower switching
• Transistor sizing (W/L) — wider devices drive harder, switch faster
• Threshold voltage — lower V_th cells are faster (LVT vs HVT)
• Temperature & process corner — SS corner at high temp is typically worst

Why It Matters in Real Chip Design

Static Timing Analysis sums propagation delays along every path to check setup and hold. When a path fails timing, engineers reduce delay by upsizing cells, using lower-V_th variants, shortening wires or restructuring logic — the daily work of physical design and STA engineers.

Propagation Delay — FAQ

What is the difference between propagation delay and contamination delay?

Propagation delay is the LONGEST time for the output to settle (used for setup checks); contamination delay is the SHORTEST time before the output starts changing (used for hold checks).

How do you reduce propagation delay?

Upsize driving cells, use low-V_th cells, reduce load capacitance, buffer long wires, and restructure logic depth. See our STA interview questions for how these appear in interviews.

Master timing from fundamentals to signoff in the Physical Design Course with real EDA tools.