Free Open-Source VLSI Learning Resources
We maintain 19 free, open-source VLSI repositories on GitHub — covering RTL design,
verification, timing, DFT, low-power, and the full RTL-to-GDSII flow. Built to grow real intuition,
not just pass an exam.
RTL & Logic Design · 5 repos
VLSI Verilog ExamplesWorked Verilog/SystemVerilog modules with testbenches.
Digital Electronics ReferenceFrom Boolean algebra to sequential logic, explained.
FSM Design PatternsSynthesizable state-machine styles, Moore vs Mealy, safe FSMs.
CDC Handling GuideMetastability, synchronizers, async FIFOs, CDC review.
Verilog CheatsheetA dense SystemVerilog quick-reference.
Digital Electronics ReferenceFrom Boolean algebra to sequential logic, explained.
FSM Design PatternsSynthesizable state-machine styles, Moore vs Mealy, safe FSMs.
CDC Handling GuideMetastability, synchronizers, async FIFOs, CDC review.
Verilog CheatsheetA dense SystemVerilog quick-reference.
Verification · 1 repo
Timing, Synthesis & Physical Design · 4 repos
DFT & Low Power · 2 repos
FPGA, Projects & Interview Prep · 5 repos
FPGA Build GuidesiCE40, ECP5 and Xilinx 7-series build walkthroughs.
B.Tech VLSI Projects8 project specs with interface, verification, and deliverables.
M.Tech VLSI ProjectsResearch templates with methodology, baselines, and metrics.
VLSI Interview PrepQ&A banks on fundamentals, RTL, and STA.
VLSI GlossaryPlain-English term bank, linked to deeper references.
B.Tech VLSI Projects8 project specs with interface, verification, and deliverables.
M.Tech VLSI ProjectsResearch templates with methodology, baselines, and metrics.
VLSI Interview PrepQ&A banks on fundamentals, RTL, and STA.
VLSI GlossaryPlain-English term bank, linked to deeper references.
Curated Links · 1 repo
All repositories are open-source under MIT / CC0 and maintained by the ChipXpert team ·
github.com/chipxpertofficial
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