OCV in VLSI: On-Chip Variation, AOCV, POCV and CRPR Explained

OCV (on-chip variation) is the difference in transistor and wire performance between different locations on the same die. Two identical gates a few millimetres apart do not have identical delays, because process, voltage and temperature are not perfectly uniform across the chip. Static timing analysis must account for this, and OCV is the family of methods that does it.

Why variation exists on one chip

• Process: lithography and etch produce slightly different channel lengths, threshold voltages and wire widths across the die. Random dopant fluctuation adds device-to-device randomness.
• Voltage: IR drop in the power grid means a gate far from a supply pad sees a lower VDD than one near it, and voltage drops change with activity.
• Temperature: hot spots under busy blocks run warmer, which changes delay (and at low voltage can even invert the usual trend: see temperature inversion).

Global PVT corners capture chip-to-chip variation: a slow die versus a fast die. They do not capture the fact that, within one die, the launch path and the capture path of a timing check may be at different speeds. OCV does.

What goes wrong without OCV

Consider a hold check. Data launched from one flip-flop must not arrive at the next before the clock edge that captures it. If the launch clock path is slightly faster than modelled and the capture clock path slightly slower, the data can arrive early and corrupt the capture. Timing signed off at a single corner with no margin can pass on paper and fail on silicon. The same applies to setup: a slow data path with a fast capture clock.

Flat OCV derating

The original method applies a fixed percentage derate to the delays of each path: launch (data) paths are made slower for setup analysis and faster for hold analysis, while capture clock paths are derated the opposite way. For example, a setup check might multiply data-path delays by 1.08 and the capture clock path by 0.95.

Flat OCV is simple but pessimistic. It assumes every cell on a long path is simultaneously at its worst, which is statistically unlikely. The pessimism grows with path depth, so deep logic cones and long clock trees get over-margined, costing area, power and design effort to close timing that was never really at risk.

Clock reconvergence pessimism removal (CRPR)

Launch and capture clock paths usually share a common segment of the clock tree up to a branch point. Derating that shared segment two different ways (slow for one, fast for the other) is physically impossible: the same buffers cannot be slow and fast at the same time. CRPR (also called CPPR) credits back the artificial difference on the common path. It is enabled in any serious OCV sign-off.

Advanced OCV (AOCV)

AOCV replaces the flat percentage with derate tables that depend on two factors:

• Depth: the number of cells in the path. Random variations average out over more stages, so the derate per cell shrinks as depth grows.
• Distance: the physical spread of the path on the die. Systematic variation grows with distance, so a path spanning a large area gets a bigger derate.

Library characterisation provides the tables for each cell type. AOCV removes much of the flat-OCV pessimism on deep paths while keeping protection on short, spread-out ones.

Parametric OCV (POCV) and statistical methods

POCV (also known as SOCV, statistical OCV) models each cell’s delay as a distribution with a mean and a standard deviation, provided by the library, and combines them statistically along the path. Instead of a single worst-case number, the tool computes the path delay at a chosen sigma (typically 3σ). POCV is the standard at advanced nodes, where variation is a large fraction of nominal delay and flat or AOCV derates would be either unsafe or hopelessly pessimistic. Full statistical static timing analysis (SSTA) goes further by tracking correlations, but POCV captures most of the benefit with far less library data.

Comparison

OCV in the physical design flow

1. Choose the OCV method and derate values or tables with the library and sign-off team; they are part of the timing constraints and sign-off methodology.
2. Enable CRPR so the common clock path is not double-counted.
3. Run setup and hold analysis at each signoff corner with OCV applied. Hold is checked at fast corners with OCV because it is the most sensitive to clock skew.
4. Fix violations: buffer insertion and sizing for setup, hold buffers on short paths, and clock tree balancing to reduce the uncommon clock path.
5. Reduce pessimism where it is legitimate: shorter uncommon clock paths, local clock gating, and accurate IR-drop-aware timing.

Read the static timing analysis guide for the checks themselves, and virtual clocks in STA for I/O timing. OCV setup and timing closure are core topics in our ASIC physical design course; see the physical design career hub for the role.

Frequently asked questions

What is OCV in VLSI?

On-chip variation: the difference in delay between identical cells and wires at different locations on the same die, caused by local process, voltage and temperature differences. STA applies derates to account for it.

What is the difference between OCV and PVT corners?

PVT corners model chip-to-chip (global) variation. OCV models variation within one chip, between the launch and capture paths of the same timing check.

What is the difference between OCV, AOCV and POCV?

OCV applies a flat derate; AOCV uses tables based on path depth and distance; POCV models each cell’s delay as a statistical distribution and combines them along the path.

What is CRPR?

Clock reconvergence pessimism removal: a correction that stops the shared part of the launch and capture clock paths from being derated two different ways at once.

Why is hold analysis more sensitive to OCV?

Hold depends on the difference between two clock arrival times and a short data path. Small variations in the clock tree are a large fraction of that margin.