Top 50 VLSI Interview Questions and Answers (2026) — ChipXpert

Q1. What is setup time and hold time in digital design?

Setup time is the minimum time the data input must be stable BEFORE the clock edge for the flip-flop to capture it correctly. Hold time is the minimum time the data must remain stable AFTER the clock edge. Setup/hold violations cause metastability and incorrect data capture.

Q2. What is metastability and how do you prevent it?

Metastability occurs when a flip-flop's input changes too close to the clock edge, causing the output to settle to an unpredictable state. Prevention: synchronizer chains (2-flop or 3-flop), Gray-code FIFOs for clock domain crossings, and avoiding asynchronous data paths into synchronous logic.

Q3. Difference between blocking (=) and non-blocking (<=) assignments in Verilog?

Blocking executes immediately and sequentially within a procedural block — use for combinational logic. Non-blocking schedules the assignment for the end of the time step — use for sequential logic in always_ff. Mixing them in the same always block creates race conditions and simulation/synthesis mismatch.

Q4. What is the difference between always_ff, always_comb, and always_latch?

always_ff enforces synthesizable sequential logic (must be triggered by an edge). always_comb enforces combinational logic with automatic sensitivity list and synthesis check for inferred latches. always_latch documents intentional latch inference. SystemVerilog-only; safer than generic always.

Q5. What is the difference between FSM Mealy and Moore machines?

Mealy: output depends on current state AND inputs. Moore: output depends only on current state. Mealy uses fewer states but outputs can glitch on input changes; Moore has cleaner synchronous outputs but more states. Most modern designs use Moore (with registered outputs).

Q6. Explain pipeline hazards and how to resolve them?

Three types: structural (resource conflict), data (RAW/WAR/WAW dependencies), control (branch). Resolutions: forwarding/bypass paths for data hazards, branch prediction + stalls for control, additional resources for structural.

Q7. What is clock skew?

Clock skew is the difference in clock arrival time at different flip-flops. Positive skew (capture clock arrives later) helps setup but hurts hold. Negative skew helps hold but hurts setup. CTS (clock tree synthesis) aims to minimize global skew while sometimes using useful skew to close timing.

Q8. Difference between latch and flip-flop?

A latch is level-sensitive (transparent when enable is asserted) — use sparingly, hard to verify, can cause race conditions. A flip-flop is edge-sensitive (captures only on clock edge) — predictable timing, easier to verify, the foundation of synchronous design.

Q9. What is a glitch and how do you prevent it?

A glitch is a transient incorrect output from combinational logic due to unequal propagation delays. Prevention: register outputs, use Gray-code encodings for state machines, avoid combinational loops, ensure single-bit changes in mutually-exclusive state transitions.

Q10. Difference between synchronous and asynchronous reset?

Synchronous: reset takes effect only on a clock edge — clean timing, but requires clock to be running. Asynchronous: reset takes effect immediately — works even without clock, but causes recovery/removal timing constraints and metastability if released near clock edge. Most modern designs use async-assert + sync-deassert.

Q11. How would you design a 4-bit synchronous up/down counter in Verilog?

Use a single always_ff @(posedge clk or negedge rst_n) block. If !rst_n, count <= 4'b0. Else: if up_down=1, count <= count + 1; else count <= count – 1. Add enable signal for power. Wrap at 4'b1111/0000.

Q12. Design an asynchronous FIFO. What's the key challenge?

Two clock domains (write and read). Use Gray-code pointers (single-bit changes only) crossed via 2-flop synchronizers. Empty/full detection compares synchronized pointers. Pointer is 1 bit wider than addressing depth (MSB for full vs empty distinction).

Q13. What is the difference between wire and reg in Verilog?

Wire: continuous net driven by assign or module output — combinational. Reg: variable that can hold value between assignments — used in always blocks. Note: reg doesn't mean register; output of an always_comb is still combinational despite being declared reg.

Q14. When would you use generate statements?

For parameterized hardware structures: arrays of modules (e.g., 32 instances of a 1-bit adder), conditional instantiation based on parameter, loop-based connection patterns. Use generate for-loops with genvar for scalability.

Q15. What are SystemVerilog interfaces and modports?

Interface bundles related signals (e.g., AXI master/slave handshake bus) into a single named connection. Modports define directional views — masters see signals from master's perspective, slaves see them from slave's perspective. Reduces port-list bloat and centralizes protocol definition.

Q16. What is a clock domain crossing (CDC) and how do you handle it?

CDC occurs when a signal moves from one clock domain to another asynchronous one. Two-flop synchronizers for single-bit. Async FIFOs or handshake for multi-bit data. CDC analysis tools (industry-standard lint and equivalence tools CDC, Meridian) verify no missed crossings.

Q17. Difference between FIFO depth and width?

Depth = number of entries (how many words the FIFO can hold). Width = bits per entry (the data bus width). Total storage = depth × width. Depth must be sized for worst-case burst behavior; width matches the data bus.

Q18. Explain wire vs logic in SystemVerilog?

SystemVerilog adds logic, which is a 4-state type that can be used in both procedural blocks (always) and continuous assignments (assign). It replaces both wire (for outputs) and reg (for procedural variables) in most cases — preferred for new SV code.

Q19. What's the difference between $display, $monitor, and $strobe?

$display prints once when called. $monitor prints whenever any of its arguments change. $strobe prints at the end of the current time step (after all NBAs settle) — useful to see "final" values at a time step.

Q20. How do you handle a reset deassertion that is asynchronous?

Asynchronous reset deassertion can cause recovery/removal time violations and metastability. Use a "reset synchronizer": flop the deassertion through 2 stages clocked by the destination domain's clock. Assertion remains asynchronous (immediate). Pattern: async-assert + sync-deassert.

Q21. What is UVM and why use it instead of SystemVerilog alone?

UVM (Universal Verification Methodology) is a standardised SystemVerilog class library that provides reusable testbench components (driver, monitor, sequencer, agent, scoreboard). Without UVM, testbenches are rewritten per project; with UVM they're portable and reusable.

Q22. Explain UVM phases.

Build, connect, end_of_elaboration, start_of_simulation, run (parallel time-consuming), extract, check, report, final. Build is bottom-up (top builds children). Connect is top-down (parents connect children). Run executes simulation. Extract/check/report happen at end-of-test.

Q23. What is the factory pattern in UVM?

uvm_factory allows you to substitute component or object types at runtime without modifying source code. Register with `factory.register()`, override with `set_inst_override` or `set_type_override`. Lets test-level configuration swap in different drivers, monitors, or sequences.

Q24. What is the role of the sequencer in UVM?

The sequencer is the arbiter between sequences and drivers. Sequences generate transactions; the sequencer manages priority and grants requests; the driver receives transactions via get_next_item/item_done handshake.

Q25. Difference between active and passive agents?

Active agent: driver + monitor + sequencer — drives stimulus to DUT. Passive agent: monitor only — observes signals without driving. Useful for hierarchical environments where one agent drives and another only observes/checks.

Q26. What is functional coverage and why is it important?

Functional coverage measures whether interesting scenarios in your verification plan were actually exercised. Covergroups, coverpoints, bins, crosses. Without coverage closure, you may have run thousands of tests but missed key scenarios. Coverage-driven verification ensures completeness.

Q27. Explain UVM register abstraction layer (RAL).

RAL provides an abstract model of the DUT's registers in the testbench, allowing high-level access (read, write, mirror) instead of low-level bus transactions. uvm_reg_block contains uvm_reg objects which contain uvm_reg_field. Adapter converts RAL operations to actual bus protocol.

Q28. What's the difference between rand and randc?

rand: pseudo-random each call, can repeat values. randc: cyclic random — generates all possible values exactly once before repeating, useful when you need full coverage of a small domain without duplicates.

Q29. How do you implement end-of-test in UVM?

Use objection mechanism: raise_objection before stimulus starts, drop_objection when stimulus is complete. Run phase ends when all objections drop. Drain time gives DUT time to settle. uvm_phase's phase_done can also be controlled directly.

Q30. What's the difference between assertions and coverage?

Assertions check that something is TRUE during simulation. Coverage measures what was EXERCISED. Both are needed: assertions catch incorrect behavior; coverage ensures you ran enough scenarios. SystemVerilog supports concurrent and immediate assertions plus covergroups.

Q31. Explain setup and hold equations.

Setup: T_clk ≥ T_clk2q + T_combinational + T_setup + T_clock_skew. Hold: T_clk2q + T_combinational ≥ T_hold + T_clock_skew. Setup determines max frequency; hold determines min path delay.

Q32. What is clock uncertainty?

Clock uncertainty is a timing margin added to account for non-ideal effects: clock jitter, skew (pre-CTS), OCV variation. Pre-CTS uncertainty is larger (~250ps); post-CTS smaller (~50ps). industry-standard timing signoff tools/industry-standard timing signoff tools use clock_uncertainty SDC commands.

Q33. What are setup and hold paths?

Setup paths: launching flop → combinational logic → capturing flop, checked at next clock edge. Hold paths: launching flop → combinational logic → capturing flop, checked at SAME clock edge. Setup uses positive clock skew helpfully; hold suffers from positive skew.

Q34. What is on-chip variation (OCV)?

OCV models the fact that two identical flip-flops in different parts of the chip see slightly different timing due to manufacturing variation, IR drop, temperature. Older flow: derate factor. Modern: AOCV (advanced OCV) uses statistical tables; even newer: parametric OCV.

Q35. What is multi-corner multi-mode (MCMM) analysis?

Modern chips operate at multiple voltages (corners) and multiple functional modes (modes). MCMM analyzes timing across all corner×mode combinations simultaneously rather than running separate analyses. Critical for advanced node signoff.

Q36. What are the major steps of the physical design flow?

Floorplanning → Power planning → Placement → Clock tree synthesis (CTS) → Routing → Signoff (STA, EM/IR, PV). Each step affects subsequent ones — iteration is normal.

Q37. What is congestion in placement and how do you fix it?

Congestion occurs when too many nets compete for routing resources in a region. Symptoms: routing failures, DRV violations. Fixes: reduce utilization, spread cells, add placement blockages, restructure logic, add buffers (if timing allows).

Q38. What is CTS and why is skew minimization important?

Clock Tree Synthesis builds the clock distribution network to balance arrival times at all flops. Lower skew → easier timing closure. Modern CTS uses useful skew strategically (route latency to help critical paths). Common structures: H-tree, mesh, hybrid.

Q39. What is ECO (Engineering Change Order)?

A late-stage design change without restarting the full flow. Functional ECO: fixes a bug post-tapeout (or pre-tapeout but late). Timing ECO: closes timing without re-synthesis. Both done in placement-aware tools to minimize churn.

Q40. Difference between IR drop and EM (Electromigration)?

IR drop: voltage drop across the power grid due to current flow — causes timing degradation. EM: current-driven migration of metal atoms causing wire thinning and eventual failure — wires sized for current density limits. Both checked at signoff (industry-standard power signoff tools, RedHawk).

Q41. What is scan insertion?

Replace every flip-flop in the design with a scan-equivalent (mux-D scan flop) that can be chained into a shift register. In test mode, scan_enable=1 connects flops as a shift register; scan_in/scan_out provide controllability and observability.

Q42. What is ATPG?

Automatic Test Pattern Generation: tools (industry-standard DFT tools, TestMAX) generate test patterns to detect stuck-at, transition, and other faults. Patterns are applied through scan chains during manufacturing test. Coverage targets typically 99%+ for stuck-at, 95%+ for transition.

Q43. What is MBIST?

Memory Built-In Self-Test: on-chip logic that tests embedded memories at full speed during manufacturing test. Uses test algorithms like March-C, March-LR. Cheaper than external memory test, finds defects ATE can't.

Q44. What is boundary scan (JTAG)?

IEEE 1149.1 standard for testing PCB-level connections via chain of boundary-scan cells on chip pins. Used for board-level fault detection, in-system programming, and debug access. JTAG TAP controller is a small state machine on each chip.

Q45. Difference between stuck-at and transition fault?

Stuck-at: a node is permanently stuck at 0 or 1 — detected by applying a value and checking propagation. Transition: a node fails to transition fast enough — detected by launch-on-shift or launch-on-capture at-speed patterns.

Q46. What is the difference between industry-standard place-and-route tools?

Both are place-and-route tools for digital designs. industry-standard PnR tools is industry-standard EDA tools's solution, industry-standard PnR tools is industry-standard EDA tools'. Methodology differences but functionally equivalent for most designs. Companies typically pick one and stick with it for tool flow consistency.

Q47. Why is industry-standard timing signoff tools the "golden" STA signoff tool?

industry-standard timing signoff tools has been the de-facto industry standard for 25+ years; foundry PDKs ship optimized SDC examples for industry-standard timing signoff tools; design teams have decades of accumulated experience. industry-standard EDA tools industry-standard timing signoff tools is gaining adoption but industry-standard timing signoff tools remains the safe signoff choice.

Q48. What is Calibre used for?

Calibre by industry-standard EDA is the industry-standard physical verification tool: DRC (design rule checks), LVS (layout vs schematic), antenna checks, ERC. Foundries provide Calibre runsets directly. Used at every chip company globally.

Q49. What's the typical chip design flow timeline?

Specification (1-3 months) → RTL design (6-12 months) → Verification (12-18 months, parallel with design) → Synthesis (1-2 months) → Physical design (3-6 months) → Signoff (1-2 months) → Tape-out → Silicon (6-12 weeks fab) → Validation (3-6 months). Total: 18-36 months for a new chip.

Q50. What languages should a VLSI engineer know besides Verilog/SV?

TCL (for EDA tool scripting — every modern tool uses TCL), Python (for automation and data analysis), Perl (legacy but still common), bash/shell (for Linux workflow), C/C++ (for understanding software side and DPI). Knowing TCL is essentially mandatory.