Hierarchical Design in VLSI: Partitioning, Budgeting and Top-Level Assembly

Hierarchical design is the practice of building a large chip as a tree of smaller blocks, each designed, verified and implemented on its own and then assembled at the next level up. It is how a design with hundreds of millions of cells becomes manageable: no tool run, no engineer and no review ever has to deal with the whole chip at once.

Flat vs hierarchical design

In a flat flow the entire netlist is one level: every cell is placed, routed and timed together. Tools see everything, so optimisation is global, but run times, memory and the cost of each iteration grow with chip size until they become unworkable. In a hierarchical flow the chip is partitioned into blocks (also called partitions or modules). Each block is implemented separately, abstracted into a model, and the top level is implemented using those models.

Hierarchy in RTL

Hierarchy begins in the HDL: modules instantiate sub-modules, and the top module instantiates everything. Good RTL hierarchy follows function (a CPU core, a memory controller, a bus fabric), keeps interfaces clean and registered, and avoids logic that straddles module boundaries, because that logic will be hard to time and to partition later. See RTL design and the HDL guide.

Hierarchy in verification

Blocks are verified in block-level testbenches with full control and visibility, and then at subsystem and chip level with the focus on integration. UVM environments are themselves hierarchical (agents inside environments inside tests) so that block-level components are reused at the top. See the UVM testbench tutorial.

Hierarchical physical design flow

1. Partitioning. Decide which RTL modules become physical partitions. Guidelines: 1 to 5 million instances per block, few and well-defined ports, natural clock and power domains, and hard macros (memories, analog IP) grouped sensibly.
2. Chip-level floorplan. Place the partitions and macros, plan the power grid, define pin locations on each partition’s boundary and route the top-level buses between them.
3. Timing budgeting. Each path that crosses a partition boundary is split: part of the clock period is budgeted to each side, and expressed as input/output delay constraints for the block.
4. Block implementation. Each partition goes through placement, clock tree synthesis, routing and optimisation independently, meeting its budget. See the physical design flow.
5. Abstraction. Each finished block is reduced to models the top level can use: a timing model (ETM or ILM), a physical abstract (LEF) showing pins and blockages, and a power model.
6. Top-level assembly. The top is implemented with the block models, top-level logic and clock distribution. Interface timing is checked; if a budget cannot be met, it is renegotiated and the affected block is re-run.
7. Full-chip signoff. Final timing, physical verification and power analysis are run on the assembled chip, often with the blocks flattened for the signoff tools only.

Timing models at block boundaries

• ETM (extracted timing model): a compact library-like model of the block’s boundary timing; fast, hides internals, less accurate for complex interface logic.
• ILM (interface logic model): keeps the netlist from each port up to the first register and removes the rest; more accurate, still much smaller than the full block.

Channel-less and abutted floorplans

Modern hierarchical designs often abut partitions with no routing channel between them, and route top-level nets over the blocks through feedthroughs. This saves area but requires careful pin planning and power-grid alignment across partition boundaries.

Benefits

• Parallel implementation by several engineers or teams.
• Bounded, predictable tool run times and memory.
• Reuse of implemented blocks as hard IP across projects and derivatives.
• Isolation of changes: a late RTL fix in one block does not force the whole chip to be re-run.
• Natural mapping of voltage and power domains to blocks.

Costs and pitfalls

• Timing budgeting is iterative; a bad budget wastes block-level effort.
• Logic that spans boundaries, or many small partitions, erodes optimisation quality.
• Pin placement and feedthrough planning take real floorplanning skill.
• Model accuracy: an ETM that misses a timing arc becomes a silicon bug if not caught at full-chip signoff.

Where you learn it

Partitioning, budgeting and top-level assembly are advanced topics in our ASIC physical design course; floorplanning fundamentals are in understanding floorplanning. See the physical design career hub for the role.

Frequently asked questions

What is hierarchical design in VLSI?

Designing a chip as a tree of blocks that are specified, verified and physically implemented separately and then assembled at the top level, instead of handling the whole chip at once.

When should a design be implemented hierarchically?

When it is too large for a flat run to finish in acceptable time or memory, when several teams must work in parallel, or when blocks will be reused as hard IP.

What is timing budgeting?

Splitting the clock period of each path that crosses a block boundary between the two blocks, so that each block can be timed on its own with input and output delay constraints.

What is the difference between ETM and ILM?

An ETM is a compact timing model of a block’s boundary behaviour; an ILM keeps the actual interface logic up to the first register for better accuracy.

Does hierarchy reduce quality of results?

Slightly, because optimisation cannot cross partition boundaries freely. Good partitioning and registered interfaces keep the loss small.