On-Chip Clock Controller (OCC) in DFT: At-Speed Testing Explained

An on-chip clock controller (OCC) is a DFT circuit that controls the clocks of a design during scan testing, so that at-speed tests can be run using the chip’s own PLL clock while the scan shifting uses a slow tester clock. Without an OCC, delay faults (transition and path-delay faults) cannot be tested at the real operating frequency, because the tester cannot supply multi-gigahertz clock pulses to every scan chain.

Why at-speed testing needs an OCC

Stuck-at testing checks logic values and can run at any speed. Transition-delay testing checks that signals arrive within one clock period, so the launch and capture clock pulses must be separated by the functional clock period: nanoseconds, not the tens of nanoseconds a tester can deliver. The functional PLL already generates that clock on-chip. The OCC’s job is to let scan shift happen on the slow tester clock, then release exactly two (or a programmable number of) fast PLL pulses for launch and capture, then return to the slow clock for the next shift.

What an OCC contains

• Clock multiplexer: selects between the tester (scan) clock and the PLL (fast) clock, with glitch-free switching.
• Pulse generator / clock chopper: produces a programmed number of fast-clock pulses after the scan-enable signal drops.
• Clock control bits: a small shift register (loaded through the scan chain) that selects how many pulses to issue and which clock domains to pulse in a given pattern.
• Synchronisers: align the scan-enable and control signals to the fast clock domain to avoid metastability.
• Bypass and test mode controls: for stuck-at mode (slow clock only), functional mode (OCC transparent) and at-speed mode.

How an at-speed pattern runs with an OCC

1. Shift: scan enable is high; the OCC passes the slow tester clock to the scan chains; the pattern, including the OCC control bits, is shifted in.
2. Launch: scan enable drops; the OCC waits for the fast clock, then issues the first pulse. The last shift (launch-on-shift) or the first capture pulse (launch-on-capture, the common choice with OCCs) creates the transition.
3. Capture: the second fast pulse, one functional period later, captures the response.
4. Shift out: scan enable rises; the slow clock returns; the response is shifted out and compared on the tester.

Where OCCs sit in the design

One OCC per clock domain, placed at the output of the PLL or clock generator and before the clock tree. In multi-clock designs, each OCC’s control bits let the pattern generator pulse one domain or several, and inter-domain paths are handled with false paths or careful pulse sequencing. OCCs are inserted during DFT insertion, before clock tree synthesis, so that the clock tree is built on the OCC output. See scan chain insertion for the surrounding flow.

Design considerations

• Glitch-free switching between clock sources is essential; a glitch corrupts every flip-flop in the domain.
• Timing: the OCC adds latency and must meet timing in both scan and functional modes; the functional path through it must not add skew.
• Scan-enable timing: scan enable is often pipelined because it fans out to every flop; the OCC must see it cleanly in the fast domain.
• PLL stability: the PLL must be locked before at-speed patterns run, and must stay locked through the slow-clock shifting.
• Power: launch and capture pulses cause large switching activity; patterns and OCC control are managed to stay within the chip’s power limits.
• Coverage: ATPG must model the OCC correctly so it knows which clocks it can pulse and when.

Learn DFT and at-speed testing

OCC insertion, at-speed ATPG and pattern debug are part of our Design for Test (DFT) course. Read fault models for why delay faults need at-speed testing, and see the DFT career hub.

Frequently asked questions

What is OCC in VLSI?

An on-chip clock controller: DFT logic that switches between the slow scan clock and the fast functional (PLL) clock and issues a programmed number of fast pulses, so delay faults can be tested at operating speed.

Why can’t the tester supply the fast clock?

Testers cannot deliver precise multi-gigahertz pulses through package pins to every clock domain; the chip’s PLL can, and the OCC controls it.

What is launch-on-capture?

An at-speed test method where the transition is launched by the first capture pulse and captured by the second, both from the fast clock; it is the usual method with OCCs.

How many OCCs does a chip need?

Typically one per test clock domain.

When is the OCC inserted?

During DFT insertion, before clock tree synthesis, so the clock tree is synthesized from the OCC’s output.