Physical Design Interview Questions and Answers (2026)

Q1. What are the major steps of the physical design flow?

Floorplanning → Power planning → Placement → Clock tree synthesis (CTS) → Routing → Signoff (STA, EM/IR, PV). Each step affects subsequent ones — iteration is normal, and a late signoff failure often means revisiting floorplan decisions made weeks earlier.

Q2. What decisions get made during floorplanning?

Die size and aspect ratio, macro/memory placement, I/O pin assignment, power ring and strap structure, and blockages for routing-sensitive regions. Good floorplanning anticipates congestion and timing problems before placement even starts — fixing a bad floorplan late is far more expensive than getting it right early.

Q3. How do you plan the power grid (power planning)?

Build a mesh of power/ground straps and rings sized for worst-case current demand, respecting IR drop and electromigration limits. Decoupling capacitors are placed near switching-heavy blocks. The grid must balance metal usage (routing resources) against voltage drop — over-provisioning wastes routing tracks, under-provisioning causes IR drop failures at signoff.

Q4. What is a macro placement strategy and why does it matter?

Macros (memories, large IP blocks) are placed first because they’re fixed-shape and hard to move later. Poor macro placement creates unroutable channels or long timing paths between macros and logic that depends on them. Common strategies: place macros near the I/O they connect to, leave routing channels between macro rows, and align macros to simplify power strap continuity.

Q5. What is congestion in placement and how do you fix it?

Congestion occurs when too many nets compete for routing resources in a region. Symptoms: routing failures, DRV (design rule violation) violations. Fixes: reduce utilization, spread cells, add placement blockages, restructure logic, add buffers (if timing allows), or adjust floorplan to give the hot region more routing layers.

Q6. What is utilization and what’s a typical target?

Utilization is the ratio of cell area to available placement area. Typical targets run 65-85% depending on design and node — too high leaves no room for routing or ECO cells, too low wastes die area and increases wire length. Memory-heavy or congestion-prone designs target the lower end of that range.

Q7. What causes placement-stage timing violations, and how are they fixed?

Long wire length between a flop pair, insufficient buffering on a high-fanout net, or cells placed far from their critical-path neighbors. Fixes: timing-driven placement re-optimization, manual cell swaps to standard cells with better drive strength, or adding repeaters along long nets.

Q8. What is a placement blockage and when do you use one?

A blockage marks an area where the placer cannot drop standard cells — used to reserve routing channels near macros, protect areas for later ECO cells, or keep clock-sensitive regions clear. Hard blockages fully exclude cells; soft/partial blockages allow some cell types through.

Q9. What is CTS and why is skew minimization important?

Clock Tree Synthesis builds the clock distribution network to balance arrival times at all flops. Lower skew → easier timing closure. Modern CTS uses useful skew strategically (routing extra latency to help a critical path) rather than blindly minimizing skew everywhere.

Q10. What clock tree topologies exist, and when is each used?

H-tree gives very low, balanced skew but costs more buffers and area — common on high-frequency designs. Mesh structures trade some skew for robustness against on-chip variation, often used on large, high-performance cores. Hybrid approaches combine a balanced backbone with local mesh in hot regions.

Q11. What is clock gating and how does it interact with CTS?

Clock gating inserts logic (an ICG cell) to stop the clock toggling a flop bank when its output isn’t needed, saving dynamic power. CTS must balance skew through the gate the same way as through a buffer, and gating-enable timing itself needs its own setup/hold checks to avoid glitches reaching the clock pin.

Q12. What is clock tree ECO and when is it needed?

A clock tree ECO adjusts buffer sizes, insertion delay, or routing after the initial CTS pass — usually triggered by a late floorplan or placement change that shifted skew outside budget. Because the clock tree touches every flop, even a small ECO here can ripple into many downstream timing paths, so it’s done cautiously and re-verified broadly.

Q13. What is the difference between global and detailed routing?

Global routing assigns each net to a coarse region/track budget across the chip without exact geometry — it estimates congestion and timing quickly. Detailed routing then lays down the actual metal shapes and vias obeying design rules. A global routing congestion map that looks clean usually means detailed routing will converge without major rework.

Q14. What is ECO (Engineering Change Order) and what types exist?

A late-stage design change without restarting the full flow. Functional ECO: fixes a logic bug post-tapeout or late pre-tapeout. Timing ECO: closes timing without full re-synthesis — swapping cell sizes, adding buffers, or adjusting placement locally. Both are done in placement-aware tools to minimize disruption to an otherwise-converged design.

Q15. Difference between IR drop and EM (electromigration)?

IR drop is the voltage drop across the power grid caused by current flow — it degrades timing margins because transistors switch slower at lower effective voltage. EM is current-driven migration of metal atoms that physically thins wires over time, eventually causing open or resistive failures. Both are checked at signoff with tools like industry-standard power signoff tools or RedHawk, and both get worse as current density rises with advanced nodes.

Q16. What is antenna effect and how is it prevented?

During fabrication, an isolated piece of metal can act as an antenna, collecting charge from plasma processes and damaging the gate oxide it connects to before the protective diode is in place. Prevention: antenna diodes, routing rule checks that limit isolated metal length per layer, and jumpering a net across layers to break up long antenna-prone segments.

Q17. What is crosstalk and when does it become a signoff concern?

Crosstalk is unwanted coupling between adjacent routed nets, causing a switching “aggressor” net to inject noise or delay onto a quiet “victim” net. It becomes a signoff concern at advanced nodes where wire spacing shrinks and coupling capacitance rises relative to ground capacitance — signoff tools report both crosstalk-induced delay and glitch risk.

Q18. What is multi-corner multi-mode (MCMM) analysis and why is it run at signoff?

Modern chips operate at multiple voltage/process corners and multiple functional modes (e.g., test mode, low-power mode, functional mode). MCMM analyzes timing across all corner×mode combinations simultaneously rather than running separate analyses, because a design that’s clean at one corner can fail at another — this is mandatory at advanced-node signoff.

Q19. What is physical verification (PV) and what does it check?

PV covers DRC (design rule checks — manufacturability), LVS (layout vs. schematic — the layout matches the intended netlist), and ERC (electrical rule checks — e.g., floating nets, missing connections). Foundries provide PV rule decks (e.g., Calibre runsets), and a chip cannot tape out with open DRC/LVS violations.

Q20. What tools are commonly used across the physical design flow?

Place-and-route: industry-standard place-and-route tools or industry-standard place-and-route tools. STA signoff: industry-standard EDA tools industry-standard timing signoff tools (industry standard for 25+ years) or industry-standard EDA tools industry-standard timing signoff tools. Power/IR-EM signoff: industry-standard EDA tools industry-standard power signoff tools or industry-standard EDA tools RedHawk. Physical verification: Calibre by industry-standard EDA. Companies typically standardize on one vendor’s flow for consistency rather than mixing tools mid-project.