Verilog Tutorial

Learn Verilog HDL from the ground up: syntax, data types, operators, always blocks, testbenches and complete working examples — every example verified in a real simulator.

• Chapter 1
  Verilog Data Types: wire, reg, Vectors and More
• Chapter 2
  Verilog Operators Explained with Examples
• Chapter 3
  Verilog if-else Statement: Syntax, Priority and Latches
• Chapter 4
  Verilog Case Statement: casez, casex and Latch Traps
• Chapter 5
  Verilog Arrays and Memories: A Practical Guide
• Chapter 6
  Verilog Parameters: parameter, localparam, and Overrides
• Chapter 7
  Verilog Testbench: Structure, Examples, Self-Checking
• Chapter 8
  Verilog Code for a 4:1 MUX: 3 Styles + Testbench
• Chapter 9
  T Flip-Flop Verilog Code with Async Reset
• Chapter 10
  D Flip-Flop Verilog Code: Async & Sync Reset
• Chapter 11
  Full Adder Verilog Code: Dataflow, Behavioral and Structural
• Chapter 12
  Half Adder Verilog Code: Dataflow and Gate-Level
• Chapter 13
  4-Bit Up/Down Counter Verilog Code (With Testbench)
• Chapter 14
  Shift Register Verilog Code: SISO, SIPO, PISO & Universal
• Chapter 15
  FSM Verilog Code: Mealy vs Moore (1011 Detector)
• Chapter 16
  Synchronous FIFO Verilog Code with Testbench
• Chapter 17
  Binary to Gray Code Verilog Code
• Chapter 18
  4-Bit ALU Verilog Code with Testbench
• Chapter 19
  UART Verilog Code: TX, RX & Loopback Testbench
• Chapter 20
  8-to-3 Priority Encoder Verilog Code with Valid Flag
• Chapter 21
  Decoder Verilog Code: 2-to-4 and 3-to-8 With Enable
• Chapter 22
  4-Bit Comparator Verilog Code: Behavioral & Structural
• Chapter 23
  1-to-4 Demultiplexer Verilog Code (Behavioral + Dataflow)
• Chapter 24
  Ring Counter & Johnson Counter Verilog Code (4-bit)
• Chapter 25
  Barrel Shifter Verilog Code (Parameterized, with Testbench)
• Chapter 26
  Mod-N Counter in Verilog: Parameterized Code + Mod-10 TB
• Chapter 27
  Switch Debounce Verilog Code: Counter-Based Debouncer
• Chapter 28
  SPI Master Verilog Code: Mode-0 with Loopback Testbench
• Chapter 29
  I2C Master Verilog Code: A Simple, Runnable Example
• Chapter 30
  AXI4-Lite Slave in Verilog: Write and Read Example
• Chapter 31
  APB Slave Verilog Code with Read/Write Testbench
• Chapter 32
  Single-Port RAM Verilog Code with Testbench
• Chapter 33
  ROM Verilog Code: Parameterized Sync and Async Examples
• Chapter 34
  Clock Divider Verilog Code: Divide-by-2, N, and Odd
• Chapter 35
  Edge Detector Verilog Code (Rising, Falling, Both)
• Chapter 36
  Gray Code Counter in Verilog: Code, Testbench, Explained
• Chapter 37
  Parity Generator and Checker in Verilog (XOR Reduction)