Clock Divider Verilog Code: Divide-by-2, N, and Odd
A clock divider turns a fast input clock into a slower one by a fixed integer ratio. It is one of the first sequential circuits every RTL engineer writes, and it shows up everywhere: generating a slow SPI or I2C clock from a system clock, building a baud-rate generator, or driving a seven-segment refresh counter. This tutorial gives you complete, runnable clock divider verilog code for three cases: divide-by-2, divide-by-N for any even N, and a divide-by-odd-N that still produces an exact 50% duty cycle. Each design ships with a self-checking testbench so you can watch the divided clock in simulation.
Everything here is plain Verilog-2005. You can build and run any example with Icarus Verilog:
iverilog -g2005 -o sim file.v && vvp sim
1. Divide-by-2: the toggle flip-flop
Dividing by 2 is the simplest case and the building block for everything else. A single flip-flop that inverts its own output on every rising edge produces a clock at exactly half the frequency with a perfect 50% duty cycle. Because the output changes once per input period, the high and low phases are each one full input period long.
// clk_div2.v -- divide the input clock by 2 (exact 50% duty cycle)
module clk_div2 (
input wire clk_in,
input wire rst_n,
output reg clk_out
);
always @(posedge clk_in or negedge rst_n) begin
if (!rst_n)
clk_out <= 1'b0;
else
clk_out <= ~clk_out;
end
endmodule
// ---- Testbench ----
module tb_clk_div2;
reg clk_in;
reg rst_n;
wire clk_out;
clk_div2 dut (
.clk_in (clk_in),
.rst_n (rst_n),
.clk_out (clk_out)
);
// 100 MHz source clock: period = 10 time units
initial clk_in = 1'b0;
always #5 clk_in = ~clk_in;
initial begin
rst_n = 1'b0;
#12 rst_n = 1'b1; // release reset after a couple of edges
end
initial begin
$monitor("t=%0t clk_in=%b clk_out=%b", $time, clk_in, clk_out);
#90 $display("Done: clk_out toggles once per rising edge of clk_in");
$finish;
end
endmodulet=0 clk_in=0 clk_out=0 t=5 clk_in=1 clk_out=0 t=10 clk_in=0 clk_out=0 t=15 clk_in=1 clk_out=1 t=20 clk_in=0 clk_out=1 t=25 clk_in=1 clk_out=0 t=30 clk_in=0 clk_out=0 t=35 clk_in=1 clk_out=1 t=40 clk_in=0 clk_out=1 t=45 clk_in=1 clk_out=0 t=50 clk_in=0 clk_out=0 t=55 clk_in=1 clk_out=1 t=60 clk_in=0 clk_out=1 t=65 clk_in=1 clk_out=0 t=70 clk_in=0 clk_out=0 t=75 clk_in=1 clk_out=1 t=80 clk_in=0 clk_out=1 t=85 clk_in=1 clk_out=0 Done: clk_out toggles once per rising edge of clk_in /var/folders/l0/gs5hnkm56g54bmxg32r6nnwr0000gn/T/tmp5li3u9d1/clk_div2.v:39: $finish called at 90 (1s) t=90 clk_in=0 clk_out=0
How it works
The always block is edge-triggered on posedge clk_in, with an active-low asynchronous reset rst_n. On each rising edge, clk_out inverts. Two input edges therefore make one full output period, so the frequency is halved. Notice the non-blocking assignment (<=) — this is mandatory inside clocked blocks to model register behaviour correctly.
2. Divide-by-N for even N
To divide by an even number, count input edges and toggle the output halfway through each output period. If you want to divide by DIV, you flip clk_out every DIV/2 input cycles. Because the toggle happens at the midpoint, the high and low phases are equal and the duty cycle stays at 50%. The parameter below defaults to 4, but you can set it to 6, 8, 10, or any even value.
// clk_div_even.v -- divide by any EVEN integer DIV, 50% duty cycle
module clk_div_even #(
parameter DIV = 4 // even, >= 2
)(
input wire clk_in,
input wire rst_n,
output reg clk_out
);
localparam HALF = DIV / 2;
reg [31:0] count;
always @(posedge clk_in or negedge rst_n) begin
if (!rst_n) begin
count <= 32'd0;
clk_out <= 1'b0;
end else if (count == HALF - 1) begin
count <= 32'd0;
clk_out <= ~clk_out; // flip output every HALF input cycles
end else begin
count <= count + 32'd1;
end
end
endmodule
// ---- Testbench ----
module tb_clk_div_even;
reg clk_in;
reg rst_n;
wire clk_out;
clk_div_even #(.DIV(4)) dut ( // divide by 4
.clk_in (clk_in),
.rst_n (rst_n),
.clk_out (clk_out)
);
initial clk_in = 1'b0;
always #5 clk_in = ~clk_in; // period 10
initial begin
rst_n = 1'b0;
#12 rst_n = 1'b1;
end
initial begin
$monitor("t=%0t clk_in=%b clk_out=%b", $time, clk_in, clk_out);
#180 $display("Done: clk_out period is 4x clk_in period");
$finish;
end
endmodulet=0 clk_in=0 clk_out=0 t=5 clk_in=1 clk_out=0 t=10 clk_in=0 clk_out=0 t=15 clk_in=1 clk_out=0 t=20 clk_in=0 clk_out=0 t=25 clk_in=1 clk_out=1 t=30 clk_in=0 clk_out=1 t=35 clk_in=1 clk_out=1 t=40 clk_in=0 clk_out=1 t=45 clk_in=1 clk_out=0 t=50 clk_in=0 clk_out=0 t=55 clk_in=1 clk_out=0 t=60 clk_in=0 clk_out=0 t=65 clk_in=1 clk_out=1 t=70 clk_in=0 clk_out=1 t=75 clk_in=1 clk_out=1 t=80 clk_in=0 clk_out=1 t=85 clk_in=1 clk_out=0 t=90 clk_in=0 clk_out=0 t=95 clk_in=1 clk_out=0 t=100 clk_in=0 clk_out=0 t=105 clk_in=1 clk_out=1 t=110 clk_in=0 clk_out=1 t=115 clk_in=1 clk_out=1 t=120 clk_in=0 clk_out=1 t=125 clk_in=1 clk_out=0 t=130 clk_in=0 clk_out=0 t=135 clk_in=1 clk_out=0 t=140 clk_in=0 clk_out=0 t=145 clk_in=1 clk_out=1 t=150 clk_in=0 clk_out=1 t=155 clk_in=1 clk_out=1 t=160 clk_in=0 clk_out=1 t=165 clk_in=1 clk_out=0 t=170 clk_in=0 clk_out=0 t=175 clk_in=1 clk_out=0 Done: clk_out period is 4x clk_in period /var/folders/l0/gs5hnkm56g54bmxg32r6nnwr0000gn/T/tmphc5f8h51/clk_div_even.v:48: $finish called at 180 (1s) t=180 clk_in=0 clk_out=0
How it works
The counter runs from 0 up to HALF - 1. When it reaches that value it resets to zero and toggles the output. For DIV = 4, HALF = 2, so the output flips every two input cycles — giving an output period of four input cycles. In the log you can confirm the output stays high for two input periods and low for two, a clean divide-by-4.
3. Divide-by-odd-N with 50% duty cycle
Odd division is the tricky one. If you simply toggle an output after an odd count, the high and low phases differ by one input period, so the duty cycle is never 50% — it comes out as something like 33% or 66%. To fix this, the output must switch on both rising and falling edges. The standard trick builds two identical divided clocks: phase A on the rising edge and phase B on the falling edge, so B is naturally shifted half an input period behind A. Each phase is held high for (DIV+1)/2 input cycles, and ANDing them trims the overlap to exactly half the output period.
// clk_div_odd.v -- divide by an ODD integer DIV with a true 50% duty cycle.
// Idea: build one divided clock on the rising edge (phase A) and an identical
// one on the falling edge (phase B, shifted half an input period). Each phase
// is high for (DIV+1)/2 input cycles out of DIV. ANDing the two trims the
// overlap to exactly DIV/2 input periods high and DIV/2 low -> 50% duty.
module clk_div_odd #(
parameter DIV = 3 // odd, >= 3
)(
input wire clk_in,
input wire rst_n,
output wire clk_out
);
reg [31:0] cnt_p, cnt_n;
reg phase_p, phase_n;
// rising-edge phase
always @(posedge clk_in or negedge rst_n) begin
if (!rst_n) begin
cnt_p <= 32'd0;
phase_p <= 1'b0;
end else begin
cnt_p <= (cnt_p == DIV-1) ? 32'd0 : cnt_p + 32'd1;
phase_p <= (cnt_p < (DIV+1)/2);
end
end
// falling-edge phase (naturally half a period behind phase_p)
always @(negedge clk_in or negedge rst_n) begin
if (!rst_n) begin
cnt_n <= 32'd0;
phase_n <= 1'b0;
end else begin
cnt_n <= (cnt_n == DIV-1) ? 32'd0 : cnt_n + 32'd1;
phase_n <= (cnt_n < (DIV+1)/2);
end
end
assign clk_out = phase_p & phase_n;
endmodule
// ---- Testbench ----
module tb_clk_div_odd;
reg clk_in;
reg rst_n;
wire clk_out;
clk_div_odd #(.DIV(3)) dut ( // divide by 3
.clk_in (clk_in),
.rst_n (rst_n),
.clk_out (clk_out)
);
initial clk_in = 1'b0;
always #5 clk_in = ~clk_in; // period 10
initial begin
rst_n = 1'b0;
#12 rst_n = 1'b1;
end
initial begin
$monitor("t=%0t clk_in=%b clk_out=%b", $time, clk_in, clk_out);
#180 $display("Done: clk_out period is 3x clk_in with 50%% duty");
$finish;
end
endmodulet=0 clk_in=0 clk_out=0 t=5 clk_in=1 clk_out=0 t=10 clk_in=0 clk_out=0 t=15 clk_in=1 clk_out=0 t=20 clk_in=0 clk_out=1 t=25 clk_in=1 clk_out=1 t=30 clk_in=0 clk_out=1 t=35 clk_in=1 clk_out=0 t=40 clk_in=0 clk_out=0 t=45 clk_in=1 clk_out=0 t=50 clk_in=0 clk_out=1 t=55 clk_in=1 clk_out=1 t=60 clk_in=0 clk_out=1 t=65 clk_in=1 clk_out=0 t=70 clk_in=0 clk_out=0 t=75 clk_in=1 clk_out=0 t=80 clk_in=0 clk_out=1 t=85 clk_in=1 clk_out=1 t=90 clk_in=0 clk_out=1 t=95 clk_in=1 clk_out=0 t=100 clk_in=0 clk_out=0 t=105 clk_in=1 clk_out=0 t=110 clk_in=0 clk_out=1 t=115 clk_in=1 clk_out=1 t=120 clk_in=0 clk_out=1 t=125 clk_in=1 clk_out=0 t=130 clk_in=0 clk_out=0 t=135 clk_in=1 clk_out=0 t=140 clk_in=0 clk_out=1 t=145 clk_in=1 clk_out=1 t=150 clk_in=0 clk_out=1 t=155 clk_in=1 clk_out=0 t=160 clk_in=0 clk_out=0 t=165 clk_in=1 clk_out=0 t=170 clk_in=0 clk_out=1 t=175 clk_in=1 clk_out=1 Done: clk_out period is 3x clk_in with 50% duty /var/folders/l0/gs5hnkm56g54bmxg32r6nnwr0000gn/T/tmpax91kemv/clk_div_odd.v:64: $finish called at 180 (1s) t=180 clk_in=0 clk_out=1
How it works
For DIV = 3, (DIV+1)/2 = 2, so each phase is high for two of every three input cycles. Phase A toggles on rising edges; phase B is the same pattern delayed by half a period because it is clocked on falling edges. Their logical AND is high only where both overlap — one and a half input periods — and low for the same span. With a 10 ns input period the output period is 30 ns, high for 15 ns and low for 15 ns: an exact 50% duty cycle, as the simulation log confirms.
Common mistakes
- Using blocking assignments in clocked blocks. Always use
<=insidealways @(posedge ...). Blocking=can create simulation-versus-synthesis mismatches and race conditions. - Expecting 50% duty from a single-edge odd divider. A counter that toggles on one edge alone cannot split an odd period evenly. You must use both edges, as shown above.
- Gating clocks with logic in real silicon. The AND gate here is fine for simulation and small FPGA designs, but ASIC flows prefer dedicated clock-gating cells or a PLL/MMCM, because combinational logic on a clock path adds glitches and skew.
- Forgetting the reset. Without a reset the counter powers up as
xin simulation and the output never settles. Always initialise sequential state. - Driving a divided clock onto general routing. On FPGAs, route generated clocks through a global clock buffer (BUFG) rather than ordinary fabric to control skew.
Quick check
Why does a toggle flip-flop give an exact 50% duty cycle when dividing by 2?
It changes state once per input rising edge, so the output is high for one full input period and low for the next. The two phases are equal in length, which is exactly 50%.
For a divide-by-8 even divider, what value does the counter count up to before toggling?
HALF - 1 = DIV/2 - 1 = 3. The counter runs 0, 1, 2, 3 and then resets and toggles, so the output flips every 4 input cycles and completes a full period every 8.
Why can’t you get a 50% duty odd divider using only the rising edge of the clock?
An odd period cannot be split into two equal integer numbers of input cycles. The only way to make the halves equal is to let the output transition on a falling edge too, shifting one phase by half an input period.
In the odd divider, what is (DIV+1)/2 for DIV = 5, and what does it control?
It is 3. It is the number of input cycles each phase clock stays high. ANDing the rising-edge and falling-edge phases then yields an output that is high for 2.5 input periods and low for 2.5, a 50% duty divide-by-5.
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