Understanding Setup and Hold Time in Sequential Logic

Introduction: why sequential logic needs a timing window

In a synchronous design, every flip-flop samples its D input at the active clock edge. A flip-flop is not an ideal sampler — internally it is a pair of latches with feedback, and that feedback needs a finite amount of time to resolve into a stable state. That physical reality is what the datasheet expresses as two numbers: setup time (T_setup) and hold time (T_hold).

Think of it as a keep-out window drawn around the clock edge. The window opens T_setup before the edge and closes T_hold after it. Data may change freely outside that window. Inside it, the data must be flat. Violate the window and the output is not simply “wrong” — it is undefined for an unbounded period, which is the definition of metastability.

Every timing constraint you will ever write, every slack number a timing report prints, and most of the physical design effort in a modern chip exists to guarantee that this one window is respected on hundreds of millions of flip-flops, across every process corner and every operating mode.

The setup check, worked through

The setup check asks a single question: does the data launched on edge N arrive at the capture flop early enough to be stable before edge N+1? It is the check that limits how fast your chip can run, because the right-hand side contains the clock period T_clk.

Setup slack is simply the required arrival time minus the actual arrival time:

Setup slack = (T_capture + T_clk − T_setup − T_uncertainty) − (T_launch + T_clk2q + T_dp)

A worked example. Take a 1 GHz clock, so T_clk = 1000 ps. Suppose the launch flop sees the clock at 120 ps and the capture flop at 140 ps (20 ps of positive skew). The launch flop’s clock-to-Q is 90 ps, the combinational data path is 700 ps, the capture flop’s setup requirement is 60 ps, and clock uncertainty is 50 ps.

• Data arrives at: 120 + 90 + 700 = 910 ps
• Data is required by: 140 + 1000 − 60 − 50 = 1030 ps
• Setup slack = 1030 − 910 = +120 ps — the path passes.

Notice that positive skew (capture clock later than launch clock) helped setup here. That is the basis of useful skew optimisation, and it is also why hold is the mirror image of setup: the same skew that relaxes setup tightens hold.

The hold check, worked through

The hold check asks the opposite question: does the data launched on edge N arrive so early that it corrupts what the capture flop is still trying to latch from edge N−1? Because both sides of the inequality reference the same clock edge, the clock period cancels out. This is the single most important consequence to internalise:

Hold violations are independent of clock frequency. You cannot fix a hold violation by slowing the clock down. A chip with hold violations is broken at every frequency, including DC.

Hold slack = (T_launch + T_clk2q + T_dp) − (T_capture + T_hold + T_uncertainty)

Using the same path as above but with the fastest-case numbers — clock-to-Q 45 ps, data path 60 ps on a short local connection, hold requirement 40 ps, hold uncertainty 20 ps:

• Data arrives at: 120 + 45 + 60 = 225 ps
• Data must not arrive before: 140 + 40 + 20 = 200 ps
• Hold slack = 225 − 200 = +25 ps — the path passes, but only just.

Had the skew been 60 ps instead of 20 ps, the requirement would have moved to 240 ps and the path would fail hold by 15 ps. Short paths between flops that sit in different clock-tree branches are where hold violations live.

Why setup and hold violations occur

Setup violations occur when the data path delay is too long — the signal arrives too late. The usual root causes are excessive combinational logic depth between flops, high fan-out nets driving weak cells, long routes forced by congestion or floorplan distance, a slow process corner combined with low voltage and high temperature, or a clock period that was simply set too aggressively for the architecture.

Hold violations occur when the data path delay is too short — the signal changes too quickly and overwrites data the capture flop has not finished latching. The usual root causes are near-zero logic between two flops (a direct Q-to-D connection is the classic case), short local routing, a fast process corner at high voltage and low temperature, and clock skew that delays the capture clock relative to the launch clock.

The asymmetry matters for planning: setup is a design problem you solve with architecture and synthesis, while hold is largely a physical problem you solve after clock tree synthesis, once real skew numbers exist.

How to fix setup violations

Setup fixes reduce the delay on the left side of the inequality, or buy time on the right side. In rough order of how early they should be attempted:

• Reduce logic depth. Restructure the RTL — pipeline the path, rebalance logic across an existing register boundary, or replace a long ripple structure with a parallel one (for example a carry-look-ahead adder instead of a ripple-carry adder). This is the highest-leverage fix and the only one that is essentially free in area and power.
• Upsize cells (gate sizing). Swap cells on the critical path for higher-drive variants so they charge their load faster. Cheap and automated, but it increases the load on the previous stage, so it can push the problem upstream.
• Swap to a lower-V_t flavour. Low-threshold cells switch faster at the cost of significantly higher leakage. Use them surgically on the worst paths, not as a blanket strategy.
• Clone high fan-out cells. Splitting a heavily loaded driver into two drivers, each serving half the sinks, cuts the capacitive load on the critical branch.
• Apply useful clock skew. Deliberately delay the capture clock to borrow time from a neighbouring, less critical stage. Powerful, but it directly tightens the hold check on the same path — never apply it without re-running hold.
• Improve placement. Move the endpoints of the critical path closer together so the route, and therefore the RC delay, shrinks. Often the real fix when the timing report shows net delay dominating cell delay.
• Relax the constraint, if it is genuinely wrong. A multicycle path or false path that was never declared will show up as a setup violation that no amount of optimisation can close. Confirm the intent with the designer before writing the exception.

How to fix hold violations

Hold fixes add delay to the data path without disturbing setup. Because hold-critical paths are by definition short, they usually have plenty of setup slack to spend:

• Insert delay buffers or delay cells. The standard fix. Libraries ship dedicated delay cells with a large delay-to-area ratio precisely for this purpose. Insert them on the data path, never on the clock.
• Downsize cells. Swapping a high-drive cell for a weaker one increases its delay. This adds no area and is preferred over buffer insertion where a suitable cell exists.
• Swap to a higher-V_t flavour. Slower and lower leakage — a hold fix that actually improves power, which is rare and worth exploiting.
• Route detouring. Deliberately lengthening a route adds delay, but it consumes routing resources and is generally a last resort.
• Fix the clock tree. If a large group of flops all fail hold against the same launch group, the real problem is skew, not the data paths. Rebalancing the clock tree fixes hundreds of endpoints at once and is far cheaper than hundreds of buffers.

A practical caution: every hold buffer you insert also consumes setup slack on that path and adds leakage. Tools will happily insert tens of thousands of them. If hold buffer count explodes, treat it as a symptom of a clock tree or floorplan problem rather than accepting the buffers.

Setup and hold across corners and modes (MCMM)

Multi-Corner Multi-Mode (MCMM) is the framework that evaluates setup and hold across every physical condition and every operational state simultaneously. A corner captures Process, Voltage and Temperature (PVT) variation together with interconnect RC variation; a mode captures a functional state such as normal operation, scan shift, scan capture, sleep or a specific DVFS operating point. The full analysis space is the cross product of the two, which is why a modern signoff run may carry dozens of scenarios.

The rule that trips up most engineers new to the flow:

• Setup is worst at the slow corner — slow process, low voltage, high temperature — because that is where data path delay is greatest.
• Hold is worst at the fast corner — fast process, high voltage, low temperature — because that is where the data path is quickest to change.

Checking hold only at the slow corner is a classic and expensive mistake: it produces a design that passes in the timing report and fails on silicon. Both checks must be run at both extremes, in every mode, because a path that is a false path in functional mode may be a real, timing-critical path in scan shift mode.

On top of corners, signoff applies on-chip variation (OCV) derates — and at advanced nodes, AOCV or POCV, which scale the pessimism by path depth and by statistical distribution instead of applying one flat percentage. The effect is to derate launch and capture paths in opposite directions so the analysis stays pessimistic where it matters without being pessimistic everywhere.

Where setup and hold get checked in the design flow

• After synthesis. Setup is checked against estimated wire loads. Hold is usually ignored at this stage because no clock tree exists yet — skew is assumed ideal.
• After placement. Setup is checked with better RC estimates. The clock is still ideal.
• After clock tree synthesis. This is the first point at which hold becomes meaningful, because real skew and real insertion delay now exist. Most hold fixing happens here and immediately after.
• After routing. Both checks run against extracted parasitics. Remaining violations are closed with timing ECOs.
• At signoff. A dedicated static timing analysis tool re-runs every check with SPEF parasitics across the full MCMM scenario set. This is the result that gates tape-out.

If you want the full picture of how these checks fit into signoff, read our complete guide to Static Timing Analysis, and our explainer on clock skew in VLSI for the skew mechanics referenced above.

Frequently asked questions

Can a hold violation be fixed by lowering the clock frequency?

No. The clock period cancels out of the hold inequality because launch and capture reference the same edge. A hold violation is a functional failure at any frequency and must be fixed in the data path or the clock tree.

What happens physically when the setup or hold window is violated?

The flip-flop enters metastability — its output hovers between logic levels for an unbounded time before resolving randomly to 0 or 1. Downstream logic may sample different values, which is why the failure often appears as intermittent, non-reproducible behaviour.

Why does positive clock skew help setup but hurt hold?

Positive skew delays the capture clock. Setup gains that delay as extra time for data to arrive; hold loses it, because the capture flop’s keep-out window has moved later while the data is still arriving at the same moment.

Which corner should hold be signed off at?

The fast corner — fast process, high voltage, low temperature — in every functional and test mode, with the appropriate OCV or POCV derates applied.

What is the difference between clock uncertainty and clock skew?

Skew is the deterministic difference in clock arrival time between two points. Uncertainty is the margin you budget for non-deterministic effects — jitter, modelling error and, before CTS, an estimate of the skew that does not yet exist.