Latch-up is a failure in CMOS circuits where a parasitic thyristor between the power supply and ground turns on and conducts a large current that does not stop until the power is removed. It can destroy a chip in milliseconds. Every CMOS process has rules and structures to prevent it, and every layout engineer is expected to know them.
Where the parasitic thyristor comes from
In a standard CMOS process the NMOS transistor sits in the p-substrate and the PMOS sits in an n-well. Those layers unintentionally form two bipolar transistors:
- A vertical PNP: PMOS source/drain (p+) as emitter, n-well as base, p-substrate as collector.
- A lateral NPN: NMOS source/drain (n+) as emitter, p-substrate as base, n-well as collector.
The collector of each feeds the base of the other, which is the structure of a PNPN thyristor (SCR) connected between VDD and VSS. The well and substrate resistances (Rwell, Rsub) sit in series with the bases. Normally both bipolars are off. If enough current flows through one of those resistances to forward-bias a base-emitter junction, that transistor turns on, feeds the other, and the pair latches into a low-impedance state.
What triggers latch-up
- Voltage overshoot or undershoot on I/O pins that drives a junction into forward bias, injecting carriers into the substrate or well. This is the most common trigger and the reason I/O cells get the most protection.
- Electrostatic discharge (ESD) events, which inject large transient currents.
- Power-supply transients and sequencing faults, for example a block powered before its well is biased.
- Ionising radiation (single-event latch-up) in space and high-altitude electronics.
- High temperature, which raises bipolar gain and substrate resistance, lowering the trigger threshold.
Effects
Once latched, the path conducts far more current than the transistors are designed for. Symptoms range from a functional lock-up that clears on power cycling to burned metal lines, fused contacts and a permanently dead chip. In products, latch-up is a reliability and safety issue, which is why it is tested for in qualification.
Prevention techniques
1. Well and substrate taps (body contacts)
Low-resistance connections from the n-well to VDD and from the p-substrate to VSS keep the bipolar bases firmly biased. Design rules specify a maximum distance from any transistor to a tap; standard-cell libraries supply well-tap cells that placement tools insert at a fixed pitch. This is the single most important measure.
2. Guard rings
Continuous rings of n+ (tied to VDD) around PMOS regions and p+ (tied to VSS) around NMOS regions collect injected carriers before they reach the parasitic bases. Double guard rings separate noisy I/O or analog blocks from core logic.
3. Spacing
Keeping n+ and p+ diffusions of different wells far apart lowers the lateral NPN gain. Latch-up design rules set minimum n+ to n-well and p+ to n-well spacings, with larger values near I/O.
4. Process measures
Epitaxial wafers (a lightly doped layer on a heavily doped substrate) reduce substrate resistance; retrograde wells reduce well resistance; trench isolation and silicon-on-insulator (SOI) remove the parasitic path altogether.
5. I/O and ESD design
Clamp diodes, series resistance and careful placement of protection devices limit how far overshoot can inject current.
6. Layout verification
Latch-up rules are checked by DRC decks alongside LVS; ERC checks catch floating wells. Well-tap and end-cap cell insertion is a standard step in the physical design flow (see end cap cells).
Latch-up testing
Qualification tests inject current into I/O pins and apply over-voltage to supply pins while monitoring supply current; a sustained rise beyond a limit indicates latch-up. Industry test methods define the injection levels and pass criteria that products are expected to meet.
Latch-up in modern processes
FinFET and lower supply voltages make latch-up less likely in core logic, but it remains a concern at I/O, in high-voltage domains, in analog and power-management blocks, and in radiation environments. The layout rules have not gone away; they are simply enforced automatically for standard cells and manually for custom blocks.
Learn layout the right way
Guard rings, taps and spacing are drawn by hand in analog and custom layout. They are part of the first exercises in our analog layout design course; the digital side (tap cells, end caps) is covered in the physical design course. See also the analog layout career hub.
Frequently asked questions
What is latch-up in simple terms?
A short circuit between power and ground created when parasitic bipolar transistors inside a CMOS chip switch on and hold each other on, until the power is cut.
What causes latch-up?
Current injected into the substrate or well, usually from I/O overshoot, ESD, supply transients or radiation, that forward-biases a parasitic bipolar junction.
How is latch-up prevented?
Well and substrate taps close to every transistor, guard rings around sensitive or noisy regions, adequate spacing between diffusions, epitaxial or SOI substrates, and protected I/O design.
What are well-tap cells?
Standard cells containing only n-well and substrate contacts, inserted at regular intervals by the placement tool so that every transistor is within the maximum allowed distance from a tap.
Does latch-up damage the chip permanently?
It can. If the current is not limited or the power is not removed quickly, metal lines and contacts can be destroyed.
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