UVM Command-Line Processor and Plusargs

The UVM command-line processor (uvm_cmdline_processor) and the built-in +uvm_* plusargs let you change a simulation’s behaviour without recompiling — pick the test, set verbosity, override the timeout, or inject a factory override, all from the simulator command line. This is what makes one compiled testbench serve an entire regression.

The essential plusargs

• +UVM_TESTNAME=my_test — choose which test run_test() builds, no recompile.
• +UVM_VERBOSITY=UVM_HIGH — global message verbosity.
• +uvm_set_verbosity=... — verbosity for one component/phase.
• +UVM_MAX_QUIT_COUNT=5 — stop after N errors.
• +uvm_set_type_override=base,derived — factory override from the command line.

Reading your own plusargs uses the processor API (reference):

uvm_cmdline_processor clp = uvm_cmdline_processor::get_inst();
string val;
if (clp.get_arg_value("+SEED_COUNT=", val))
  `uvm_info("CFG", $sformatf("seed count = %s", val), UVM_LOW)

// +UVM_TESTNAME selects the test with no recompile:
//   simv +UVM_TESTNAME=error_test +UVM_VERBOSITY=UVM_HIGH

Because the test name, verbosity, overrides and limits are all runtime arguments, a regression script launches hundreds of distinct runs from a single compiled image — changing only the command line per run. That is the practical reason UVM testbenches are compiled once and driven entirely by plusargs.