Verilog Code for a Decoder: 2:4 and 3:8 Decoders with Testbench

A decoder is a combinational circuit that activates exactly one of 2ⁿ outputs for each n-bit input code. Decoders select memory rows, enable peripherals, drive displays and implement arbitrary logic functions. Below are a 2:4 decoder and a 3:8 decoder in Verilog, written three different ways, with a self-checking testbench.

Truth table of a 2:4 decoder with enable

Method 1: shift operator (most compact)

module decoder2to4 (
  input  wire       en,
  input  wire [1:0] a,
  output wire [3:0] y
);
  assign y = en ? (4'b0001 << a) : 4'b0000;
endmodule

Shifting a single 1 left by the input value places it in the selected position. This style scales to any size with a parameter.

Method 2: case statement (most readable)

module decoder2to4_case (
  input  wire       en,
  input  wire [1:0] a,
  output reg  [3:0] y
);
  always @* begin
    y = 4'b0000;                 // default: no output active
    if (en)
      case (a)
        2'b00: y = 4'b0001;
        2'b01: y = 4'b0010;
        2'b10: y = 4'b0100;
        2'b11: y = 4'b1000;
      endcase
  end
endmodule

The default assignment before the if guarantees every path assigns y, so no latch is inferred.

Method 3: gate-level (shows the logic)

module decoder2to4_gates (
  input  wire       en,
  input  wire [1:0] a,
  output wire [3:0] y
);
  wire na0 = ~a[0];
  wire na1 = ~a[1];
  assign y[0] = en & na1  & na0;
  assign y[1] = en & na1  & a[0];
  assign y[2] = en & a[1] & na0;
  assign y[3] = en & a[1] & a[0];
endmodule

Each output is an AND of the enable and one minterm of the inputs. Synthesis produces this structure from any of the three descriptions.

Parameterised N-to-2^N decoder

module decoder #(parameter N = 3) (
  input  wire          en,
  input  wire [N-1:0]  a,
  output wire [(1<<N)-1:0] y
);
  assign y = en ? ({{((1<<N)-1){1'b0}}, 1'b1} << a) : {(1<<N){1'b0}};
endmodule

Instantiate with decoder #(.N(3)) for a 3:8 decoder or #(.N(5)) for a 5:32 decoder.

3:8 decoder from two 2:4 decoders

A larger decoder can be built hierarchically: the most significant input bit selects which smaller decoder is enabled.

module decoder3to8_hier (
  input  wire       en,
  input  wire [2:0] a,
  output wire [7:0] y
);
  decoder2to4 lo (.en(en & ~a[2]), .a(a[1:0]), .y(y[3:0]));
  decoder2to4 hi (.en(en &  a[2]), .a(a[1:0]), .y(y[7:4]));
endmodule

Self-checking testbench

`timescale 1ns/1ps
module tb_decoder;
  reg        en;
  reg  [2:0] a;
  wire [7:0] y;
  integer i, errors = 0;

  decoder #(.N(3)) dut (.en(en), .a(a), .y(y));

  initial begin
    en = 0; a = 3'd5; #5;
    if (y !== 8'b0) begin errors = errors + 1; $display("FAIL: output active with en=0"); end

    en = 1;
    for (i = 0; i < 8; i = i + 1) begin
      a = i; #5;
      if (y !== (8'b1 << i)) begin
        errors = errors + 1;
        $display("FAIL a=%0d y=%b expected %b", i, y, 8'b1 << i);
      end
    end
    if (errors == 0) $display("PASS: decoder tests passed");
    else             $display("FAIL: %0d errors", errors);
    $finish;
  end
endmodule

Where decoders are used

• Memory address decoding: the row decoder of an SRAM selects one word-line from the address bits (see SRAM memory design).
• Peripheral chip select: high address bits select which device responds on a bus.
• Instruction decoding in processors.
• Seven-segment and display drivers (a BCD-to-seven-segment decoder is a special case with multiple outputs active).
• Implementing logic functions: any function can be built from a decoder plus OR gates, since each output is a minterm.

Related circuits

An encoder does the reverse (2ⁿ inputs to an n-bit code); a priority encoder handles multiple active inputs. A demultiplexer is a decoder whose enable is used as the data input. These are standard questions in digital electronics interviews.

Practise RTL design

Small blocks like decoders, multiplexers and the ALU are the first exercises in our RTL design course. Learn to verify them with the Verilog testbench tutorial.

Frequently asked questions

What is a decoder in digital electronics?

A combinational circuit with n inputs and up to 2ⁿ outputs that activates exactly one output for each input combination.

What is the simplest way to write a decoder in Verilog?

assign y = en ? (1 << a) : 0; with appropriate widths: shift a single 1 by the input value.

How do I avoid latches in a case-based decoder?

Assign a default value to the output before the case statement, so every path through the always block assigns it.

How is a 3:8 decoder built from 2:4 decoders?

Use two 2:4 decoders; the most significant input bit, combined with the enable, selects which one is active.

What is the difference between a decoder and a demultiplexer?

Structurally the same circuit; a demultiplexer uses the enable input as the data input and routes it to the selected output.