Digital electronics questions open almost every VLSI interview, for freshers and for experienced engineers. Interviewers use them to check whether you understand how logic actually works before they move on to RTL, verification or physical design. Below are the questions that come up most often, with short answers you should be able to expand on.
Number systems and codes
1. Convert 1011 0110 (binary) to decimal and hexadecimal.
Decimal 182; hexadecimal B6.
2. What is two’s complement and why is it used?
A way to represent negative numbers by inverting all bits and adding 1. It lets one adder handle addition and subtraction with no special sign logic, and there is only one representation of zero.
3. What is the range of an 8-bit two’s complement number?
−128 to +127.
4. What is Gray code and where is it used?
A code in which consecutive values differ in exactly one bit. It is used in rotary encoders and for passing counters across clock domains, because only one bit changes at a time.
5. What is BCD?
Binary-coded decimal: each decimal digit is stored in four bits (0000 to 1001). Used where decimal display or arithmetic is required.
Logic gates and Boolean algebra
6. Which gates are universal and why?
NAND and NOR. Any Boolean function can be built from either one alone.
7. State De Morgan’s theorems.
(A·B)̄ = Ā + B̄ and (A + B)̄ = Ā·B̄. They convert between AND-form and OR-form and are used constantly in gate conversion.
8. How many NAND gates are needed to make an XOR gate?
Four.
9. What is a K-map and what is its limit?
A Karnaugh map is a grid for simplifying Boolean functions by grouping adjacent 1s. Practical up to about five or six variables; beyond that, tools use algorithmic minimisation.
10. What is the difference between SOP and POS?
Sum of products ORs together AND terms; product of sums ANDs together OR terms. See SOP vs POS.
11. What are don’t-care conditions?
Input combinations that never occur or whose output does not matter. They can be set to 0 or 1 to simplify the logic.
Combinational circuits
12. What is the difference between a combinational and a sequential circuit?
Combinational output depends only on current inputs; sequential output also depends on stored state and is usually clocked. See combinational circuits.
13. How does a full adder differ from a half adder?
A half adder adds two bits and gives sum and carry; a full adder also takes a carry-in. Sum = A ⊕ B ⊕ Cin; Cout = AB + Cin(A ⊕ B).
14. What is a ripple-carry adder’s main drawback and how is it solved?
The carry propagates through every stage, so delay grows linearly with width. Carry-lookahead, carry-select and prefix adders compute carries in parallel.
15. What is a multiplexer? How do you build a 4:1 mux from 2:1 muxes?
A mux selects one of several inputs using select lines. Three 2:1 muxes: two in the first stage selected by S0, one in the second selected by S1.
16. Implement an AND gate using a 2:1 mux.
Connect A to the select, 0 to the input chosen when select = 0, and B to the input chosen when select = 1. Output = A·B.
17. What is the difference between a decoder and a demultiplexer?
Structurally similar. A decoder activates one of 2n outputs for an n-bit code; a demux routes one data input to one of several outputs. A decoder with an enable input works as a demux.
18. What is a priority encoder?
An encoder that outputs the code of the highest-priority active input when several inputs are active at once.
19. What is a static hazard?
A glitch on an output that should stay constant, caused by unequal path delays. Removed by adding a redundant consensus term or by registering the output.
Sequential circuits
20. What is the difference between a latch and a flip-flop?
A latch is level-sensitive and transparent while its enable is active; a flip-flop is edge-triggered and captures its input only on the clock edge. Flip-flops are used in synchronous design; unintended latches are a common RTL bug.
21. Define setup time and hold time.
Setup: the minimum time data must be stable before the clock edge. Hold: the minimum time data must stay stable after the edge. Violating either can cause metastability.
22. How do you convert a JK flip-flop into a D flip-flop? Into a T flip-flop?
D: connect D to J and D̄ to K. T: tie J and K together as T.
23. What is the maximum clock frequency of a design?
1 / (tclk-to-q + tlogic,max + tsetup), ignoring skew. Clock skew and jitter reduce it further.
24. What is the difference between synchronous and asynchronous reset?
Synchronous reset takes effect only on a clock edge and is treated as data by timing tools; asynchronous reset acts immediately and needs its release synchronised to avoid recovery/removal violations.
25. What is the difference between a ripple counter and a synchronous counter?
In a ripple counter each flip-flop is clocked by the previous one, so it is slow and glitchy. In a synchronous counter all flip-flops share the clock and next-state logic computes each bit.
26. How many flip-flops are needed for a mod-10 counter?
Four, since 23 = 8 < 10 ≤ 24 = 16.
27. What is the difference between a ring counter and a Johnson counter?
A ring counter feeds the last output straight back to the first and has n states for n flip-flops; a Johnson (twisted-ring) counter feeds back the inverted output and has 2n states.
28. What is a finite state machine? Moore vs Mealy?
A sequential circuit with a defined set of states and transitions. Moore outputs depend only on the state; Mealy outputs depend on state and inputs, so they can respond one cycle earlier but may glitch.
29. What is metastability and how do you avoid it?
An undefined output state when a flip-flop’s setup or hold time is violated, typically at clock-domain crossings. Mitigated with two-flop synchronisers, handshakes or asynchronous FIFOs.
30. What is clock skew?
The difference in clock arrival time at two flip-flops. Positive skew helps setup and hurts hold; negative skew does the opposite.
CMOS and timing
31. Why is CMOS preferred over other logic families?
Near-zero static power, high noise margins, rail-to-rail output and good scalability. See the CMOS inverter.
32. Why is the PMOS wider than the NMOS in a CMOS gate?
Hole mobility is lower, so the PMOS needs more width to match the NMOS drive and balance rise and fall times.
33. What is propagation delay?
The time from an input transition to the corresponding output transition, usually measured at 50% points. See propagation delay.
34. What is noise margin?
The amount of noise a logic input can tolerate without misreading the level: NMH = VOH − VIH, NML = VIL − VOL. See noise margin.
35. What is fan-in and fan-out?
Fan-in is the number of inputs a gate has; fan-out is the number of gate inputs one output drives. Large fan-out increases delay.
36. What are the sources of power dissipation in CMOS?
Dynamic switching power (αCV2f), short-circuit power during transitions, and static leakage.
Memory and miscellaneous
37. What is the difference between SRAM and DRAM?
SRAM stores a bit in a six-transistor cross-coupled cell and needs no refresh; it is fast and used for caches. DRAM stores charge on a capacitor with one transistor, needs refresh, and is denser and cheaper.
38. What is a tri-state buffer used for?
To let several drivers share one bus; its output can be high-impedance so that only one driver is active at a time.
39. What is the difference between a shift register and a counter?
A shift register moves data one position per clock; a counter steps through a numeric sequence. A LFSR is a shift register with feedback that generates pseudo-random sequences.
40. Design a 2-bit comparator.
Outputs A>B, A=B, A<B. A=B is the AND of the XNOR of each bit pair; A>B = A1B1̄ + (A1 ⊙ B1)A0B0̄; A<B is the complement of the other two.
How to prepare
Work each answer out on paper, not just read it, and draw the circuit for questions 13 to 19 and 25 to 28 until you can do it in two minutes. Then move to Verilog interview questions, STA interview questions and the full VLSI interview question bank. If the fundamentals feel shaky, our beginner VLSI course starts from digital electronics, and every track includes mock interviews.
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