Moore’s Law in VLSI: What It Says, Why It Slowed and What Comes Next

Moore’s law is the observation, made by Gordon Moore in 1965, that the number of transistors on an integrated circuit doubles roughly every two years. For five decades it described, and drove, the progress of VLSI: each new process node made transistors smaller, cheaper and faster, and chips grew from thousands of transistors to tens of billions. Today classic scaling has slowed, and the industry keeps the trend alive with new transistor structures, 3D integration and design techniques.

What Moore actually said

In 1965 Moore noted that the most cost-effective number of components per chip had doubled every year and predicted it would continue; in 1975 he revised the rate to doubling every two years. It is an economic and engineering observation, not a law of physics. It held because the industry planned around it: process roadmaps, equipment investment and design tools were all built on the expectation of the next node arriving on schedule.

Dennard scaling: why smaller used to mean better in every way

Through the 1970s to the early 2000s, shrinking a transistor’s dimensions by a factor k also reduced its voltage by k, so power density stayed constant while speed rose and area fell. This is Dennard scaling. Each node delivered more transistors, higher clock frequency and the same power per unit area, which is why processors went from MHz to GHz. See Dennard scaling.

Where scaling ran into limits

• Leakage. Below about 90 nm, threshold voltages could not keep falling without transistors leaking when off. Supply voltage stopped scaling, so power density rose. Dennard scaling ended around 2005; clock frequencies flattened near a few GHz.
• Short-channel effects. At short gate lengths the gate loses control of the channel. FinFETs (from 22 nm) wrapped the gate around a vertical fin to restore control; gate-all-around nanosheets (from the 3 nm class) wrap it completely.
• Lithography. Printing features smaller than the wavelength of light required immersion lithography, multiple patterning and finally extreme ultraviolet (EUV), each adding cost.
• Interconnect. Wires did not scale as well as transistors; resistance and capacitance of narrow wires now dominate delay and power on long paths.
• Variability. With a few dozen atoms across a channel, random variation between transistors is large, which is why on-chip variation analysis became essential.
• Cost. The cost per wafer at each new node rises steeply; the cost per transistor, which Moore’s law was really about, no longer falls as reliably.

How the industry keeps the trend going

Read system-technology co-optimisation for how these combine.

What Moore’s law means for VLSI engineers

• Design complexity grows every generation. Billions of transistors need hierarchical design, reuse of IP and heavy automation; see hierarchical design.
• Power, not transistor count, is the limit. Low-power design (clock and power gating, multi-voltage, DVFS) is now core to every project.
• Verification effort grows faster than design size, which is why verification engineers outnumber designers.
• Physical effects dominate at advanced nodes: variation, electromigration, IR drop and signal integrity are part of digital design, not just analog.
• Specialised architectures create new roles in accelerator design, chiplet integration and packaging-aware design.

Is Moore’s law dead?

Transistor density still increases, but more slowly, at higher cost, and increasingly through packaging and architecture rather than the transistor alone. The two-year doubling of economical transistor count on a single die is no longer reliable; the industry’s ability to deliver more capable chips each generation continues by other means. For an engineer, the practical answer is that the skills in demand have shifted toward power, variation, 3D integration and architecture, and away from simply riding the next node.

Learn the technology behind the trend

Our beginner VLSI course covers CMOS fundamentals and the design flow; the physical design course deals with the advanced-node effects described above. See also CMOS technology in VLSI and FinFET technology.

Frequently asked questions

What is Moore’s law in VLSI?

The observation that the number of transistors on an integrated circuit doubles about every two years, which drove the scaling of VLSI technology for decades.

Is Moore’s law a physical law?

No. It is an empirical observation and an industry planning target, not a law of nature.

What is the difference between Moore’s law and Dennard scaling?

Moore’s law is about transistor count per chip; Dennard scaling is about keeping power density constant as transistors shrink. Dennard scaling ended around 2005; Moore’s law has slowed but continued.

Why has Moore’s law slowed down?

Leakage, short-channel effects, lithography limits, interconnect scaling, variability and rising cost per wafer make each new node harder and more expensive.

How does the industry continue to improve chips?

New transistor structures, design-technology co-optimisation, 3D stacking and chiplets, specialised architectures and advanced packaging.