Combinational Logic and the Full Adder

Combinational logic is any circuit whose output depends only on the present inputs — no memory, no clock. Give it the same inputs and it always gives the same outputs, after a propagation delay. Adders, multiplexers, decoders, comparators and ALUs are all combinational.

Building block: the full adder

A full adder adds three bits (a, b, and a carry-in) and produces a sum and a carry-out. Chain n of them and you have an n-bit ripple-carry adder — the simplest way to add binary numbers in hardware. Sum is a^b^cin; carry-out is set when at least two inputs are 1.

module full_adder(input a, b, cin, output sum, cout);
  assign sum  = a ^ b ^ cin;
  assign cout = (a & b) | (b & cin) | (a & cin);
endmodule

module tb;
  reg [1:0] a, b; reg cin;
  wire s0, c0, s1, c1;
  full_adder fa0(a[0], b[0], cin, s0, c0);  // bit 0
  full_adder fa1(a[1], b[1], c0,  s1, c1);  // bit 1, carry chained
  initial begin
    a=2'b01; b=2'b11; cin=0; #1
    $display("%0d + %0d = %b%b%b  (cout sum1 sum0)", a, b, c1, s1, s0);
    a=2'b11; b=2'b11; cin=0; #1
    $display("%0d + %0d = %b%b%b  (cout sum1 sum0)", a, b, c1, s1, s0);
    $finish;
  end
endmodule
1 + 3 = 100  (cout sum1 sum0)
3 + 3 = 110  (cout sum1 sum0)

Notice there is no always block and no clock — just assign statements wiring gates together. That is the signature of combinational logic.

Check yourself

What single property defines a combinational circuit?

Its outputs are a pure function of its current inputs only — it holds no state and depends on no clock. The same inputs always produce the same outputs (after propagation delay).

In a ripple-carry adder, what limits its speed?

The carry has to ripple through every full adder from bit 0 to the top bit before the result is valid, so delay grows linearly with width. Faster adders (carry-lookahead, carry-select) compute carries in parallel.

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