Timing: Setup, Hold and Metastability
Flip-flops only capture data reliably if that data is stable around the clock edge. Two windows define this: setup time (the data must be steady for this long before the edge) and hold time (it must stay steady for this long after). Violate either and the flip-flop can go metastable.
Setup, hold and the clock period
Between two flip-flops sits combinational logic. For the capturing flip-flop to meet setup, the clock period must satisfy:
T_clk ≥ T_cq + T_logic + T_setup + T_skew
where Tcq is the launch flop’s clock-to-Q delay, Tlogic the longest combinational path between them, and Tskew the difference in clock arrival. This single inequality is what static timing analysis (STA) checks on every path in a chip, and it is why the critical path — the slowest logic path — sets the maximum clock frequency.
Metastability
If setup or hold is violated, the flip-flop output can hover at an invalid level between 0 and 1 for an unbounded time before randomly resolving. Inside one clock domain, STA guarantees this never happens. It becomes a real risk only when a signal crosses from one clock to an asynchronous one — the subject of the next chapter.
Check yourself
Write the setup-time constraint that sets a design’s maximum clock frequency.
T_clk ≥ T_cq + T_logic + T_setup + T_skew. The longest (critical) path’s T_logic dominates; the minimum clock period is this sum, so f_max = 1 / T_clk.
What is metastability and when can it occur?
A flip-flop output lingering at an undefined level between 0 and 1 after a setup/hold violation, resolving to a random value after an unbounded delay. It occurs when data changes too close to the clock edge — in practice, when an asynchronous signal is sampled without synchronisation.
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