Counters and Registers

Stack flip-flops together and give them a job, and you get the two most common sequential blocks in any chip: registers (that store a word) and counters (that step through a sequence of values). Program counters, address generators, timers, and baud-rate dividers are all counters.

A synchronous up-counter

A counter is a register whose next value is its current value plus one, computed by combinational logic and captured each clock. Adding an enable and a synchronous reset gives a practical, synthesizable counter:

module counter #(parameter W = 4) (
  input clk, rst_n, en,
  output reg [W-1:0] count);
  always @(posedge clk or negedge rst_n)
    if      (!rst_n) count <= 0;
    else if (en)     count <= count + 1'b1;   // wraps naturally at 2^W
endmodule

module tb;
  reg clk=0, rst_n=0, en=1; wire [3:0] count;
  counter #(.W(4)) u(clk, rst_n, en, count);
  always #5 clk = ~clk;
  integer i;
  initial begin
    #3 rst_n = 1;
    for (i=0;i<18;i=i+1) begin @(posedge clk); #1 $write("%0d ", count); end
    $display("n4-bit counter wrapped from 15 back to 0");
    $finish;
  end
endmodule
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 
4-bit counter wrapped from 15 back to 0

The counter wraps from 15 back to 0 on its own because a 4-bit register cannot hold 16 — the carry out is simply discarded. Choosing the width W sets the modulus (2W); for a non-power-of-two modulus you add a comparator that resets the count at the target value.

Check yourself

How do you make a counter that counts modulo-10 (0–9) instead of modulo-16?

Add combinational logic that resets the count to 0 when it reaches 9 (i.e. if count == 9, next = 0, else count+1). This is a BCD/decade counter; the width stays 4 bits but the sequence is forced to wrap early.

What is the difference between a synchronous and a ripple (asynchronous) counter?

In a synchronous counter every flip-flop is clocked by the same clock, so all bits update together — clean timing. In a ripple counter each stage clocks the next, so bits update in sequence with accumulating delay and transient wrong values; it is simpler but poor for fast or timing-critical designs.

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