Finite State Machines: Moore vs Mealy

A finite state machine (FSM) is the standard way to describe control logic: a small set of named states, rules for moving between them based on inputs, and outputs driven by the state. Protocol controllers, arbiters, and the control unit of a CPU are all FSMs.

Moore vs Mealy

In a Moore machine the outputs depend only on the current state — they are stable and glitch-free, changing only at clock edges. In a Mealy machine outputs depend on the state and the current inputs, so they can react one cycle sooner but may glitch with the inputs. The three-block coding style below (state register, next-state logic, output logic) is the industry-standard, synthesis-friendly template.

This Moore FSM detects the input sequence 1 0 1 and pulses found for one cycle — the testbench feeds a bit stream and prints when the pattern completes:

module seq101(input clk, rst_n, x, output found);
  localparam S0=2'd0, S1=2'd1, S10=2'd2, S101=2'd3;
  reg [1:0] state, nxt;
  always @(posedge clk or negedge rst_n)        // 1: state register
    if (!rst_n) state <= S0; else state <= nxt;
  always @(*) case (state)                      // 2: next-state logic
    S0:   nxt = x ? S1  : S0;
    S1:   nxt = x ? S1  : S10;
    S10:  nxt = x ? S101: S0;
    S101: nxt = x ? S1  : S10;
    default: nxt = S0;
  endcase
  assign found = (state == S101);               // 3: Moore output (state only)
endmodule

module tb;
  reg clk=0, rst_n=0, x=0; wire found;
  seq101 u(clk, rst_n, x, found);
  always #5 clk = ~clk;
  reg [9:0] stream = 10'b11_0_1_0_1_0_1; integer i;
  initial begin
    #3 rst_n = 1;
    for (i=9;i>=0;i=i-1) begin
      x = stream[i]; @(posedge clk); #1
      if (found) $display("t=%0t  '101' detected", $time);
    end
    $finish;
  end
endmodule

t=56  '101' detected
t=76  '101' detected
t=96  '101' detected

Check yourself

When would you choose a Moore machine over a Mealy machine?

When you need glitch-free outputs that are stable for a full clock cycle and change only at edges — e.g. driving another synchronous block or an external interface. Moore outputs depend only on the registered state, so they can’t glitch with the inputs the way Mealy outputs can.

What are the three blocks of the standard FSM coding style and why separate them?

A clocked state register, a combinational next-state block, and a combinational (or registered) output block. Separating them makes the design readable, keeps next-state logic purely combinational, and maps cleanly to what synthesis expects — avoiding accidental latches and races.

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