SystemVerilog Operators: Wildcard, inside, Streaming
SystemVerilog keeps every Verilog operator and adds a set aimed at verification and clean RTL: wildcard equality, set membership, and stream operators. Knowing them removes a lot of boilerplate loops and bit-fiddling.
Wildcard equality and inside
The wildcard equality ==? treats x/z bits in the right operand as don’t-cares — ideal for opcode decoding. The inside operator tests set and range membership in one expression, replacing a chain of || comparisons.
module tb;
logic [7:0] op;
initial begin
op = 8'b1010_0011;
// match top nibble 1010, ignore low nibble
$display("op ==? 1010xxxx : %b", (op ==? 8'b1010_xxxx));
op = 8'd7;
$display("op inside {1,3,7} : %b", (op inside {1,3,7}));
$display("op inside [5:9] : %b", (op inside {[5:9]}));
$display("op inside {[0:3],[10:20]} : %b", (op inside {[0:3],[10:20]}));
$finish;
end
endmoduleop ==? 1010xxxx : 1
op inside {1,3,7} : 1
op inside [5:9] : 1
op inside {[0:3],[10:20]} : 0
- /var/folders/l0/gs5hnkm56g54bmxg32r6nnwr0000gn/T/tmpwqftf7ep/tb.sv:11: Verilog $finishStream operators
The streaming operators {>>{}} and {<<{}} pack and unpack bits — reversing byte order or serialising a struct into a byte array becomes one line.
module tb;
logic [31:0] word = 32'hDE_AD_BE_EF;
logic [7:0] bytes [4];
initial begin
// unpack word (MSB-first) into a byte array
{>>{bytes}} = word;
$display("bytes = %h %h %h %h", bytes[0], bytes[1], bytes[2], bytes[3]);
// reverse the byte order by streaming little-endian
$display("byte-reversed = %h", {<<8{word}});
$finish;
end
endmodulebytes = de ad be ef byte-reversed = efbeadde - /var/folders/l0/gs5hnkm56g54bmxg32r6nnwr0000gn/T/tmp3sy91kpq/tb.sv:10: Verilog $finish
Check yourself
What is the difference between <code>==</code> and <code>==?</code> in SystemVerilog?
Plain == compares all bits and yields x if either operand has x/z. The wildcard ==? treats x/z bits in the right-hand operand as don’t-cares, so it matches a pattern — useful for decoding opcodes where some bits are irrelevant.
Rewrite <code>if (a==2 || a==5 || (a>=8 && a<=11))</code> using <code>inside</code>.
if (a inside {2, 5, [8:11]}) — set members and ranges combine in one brace list.
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