Parameterized Classes (Class Templates)

A parameterized class is a class template: write the logic once and specialise it by type or value. This is how reusable verification components — generic drivers, scoreboards, and the whole UVM library — are built without copy-pasting per data type.

Type and value parameters

Parameters can be values (int N) or types (type T). The class below is a generic fixed-depth stack that works for any element type:

module tb;
  class Stack #(type T = int, int DEPTH = 4);
    local T mem[$];
    function bit push(T x);
      if (mem.size() == DEPTH) return 0;   // full
      mem.push_back(x); return 1;
    endfunction
    function bit pop(output T x);
      if (mem.size() == 0) return 0;        // empty
      x = mem.pop_back(); return 1;
    endfunction
    function int size(); return mem.size(); endfunction
  endclass

  initial begin
    Stack #(int, 3) s = new();
    int v;
    $display("push 10,20,30 ok=%b%b%b", s.push(10), s.push(20), s.push(30));
    $display("push 40 (full) ok=%b", s.push(40));   // should fail
    void'(s.pop(v)); $display("pop -> %0d, size now %0d", v, s.size());
    $finish;
  end
endmodule

push 10,20,30 ok=111
push 40 (full) ok=0
pop -> 30, size now 2
- /var/folders/l0/gs5hnkm56g54bmxg32r6nnwr0000gn/T/tmphjb2kmzh/tb.sv:21: Verilog $finish

Check yourself

Why are parameterized classes essential to a framework like UVM?

They let one implementation serve every data type and configuration. UVM’s components and transactions are type-parameterized so you reuse the same driver/monitor/sequencer logic for any transaction type, specialising it at instantiation instead of rewriting it.

What kinds of parameters can a SystemVerilog class take?

Value parameters (e.g. int DEPTH = 4) and type parameters (e.g. type T = int). A specialization like Stack#(byte, 8) fixes both, producing a distinct class type.

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