always_ff, always_comb, always_latch and final

Plain Verilog has one always block for everything, and it is easy to accidentally describe a latch or mismatch simulation and synthesis. SystemVerilog adds intent-declaring procedural blocks — always_ff, always_comb, always_latch — that let the tools check you got what you meant.

Say what you mean

always_comb is combinational: it has an automatic sensitivity list and the tool errors if the logic implies memory. always_ff is a clocked register and documents the clock/reset. always_latch declares an intentional latch. initial still runs once at time 0; SystemVerilog adds final, which runs once at end of simulation — handy for printing summaries.

module tb;
  logic clk=0, rst_n=0;
  logic [3:0] d, q, doubled;
  always #5 clk = ~clk;

  always_comb doubled = d << 1;          // pure combinational, checked

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) q <= '0;                  // clocked register
    else        q <= doubled;

  initial begin
    d = 4'd3; #3 rst_n = 1;
    repeat (3) @(posedge clk);
    #1 $display("d=%0d doubled=%0d q=%0d", d, doubled, q);
    $finish;
  end
  final $display("final block: simulation finished at t=%0t", $time);
endmodule

d=3 doubled=6 q=6
- /var/folders/l0/gs5hnkm56g54bmxg32r6nnwr0000gn/T/tmpa100_inz/tb.sv:16: Verilog $finish
final block: simulation finished at t=26