Weighted Randomisation: randcase and $urandom_range

Constrained-random verification needs more than uniform randomness — you want weighted choices so realistic traffic (mostly reads, occasional errors) emerges. SystemVerilog gives you randcase for weighted branch selection and $urandom_range for bounded values, usable anywhere without a full class constraint.

Weighted selection with randcase

Each randcase item has a weight; the probability of a branch is its weight divided by the total. The example generates 10000 transactions that are 70% read, 25% write, 5% error, and prints the measured distribution — which converges on the weights:

module tb;
  int reads=0, writes=0, errs=0;
  initial begin
    for (int i = 0; i < 10000; i++) begin
      randcase
        70: reads++;     // weight 70
        25: writes++;    // weight 25
         5: errs++;      // weight 5
      endcase
    end
    $display("reads=%0d (~70%%)  writes=%0d (~25%%)  errs=%0d (~5%%)",
             reads, writes, errs);
    $display("random value in [10:20] = %0d", $urandom_range(10,20));
    $finish;
  end
endmodule

reads=7034 (~70%)  writes=2440 (~25%)  errs=526 (~5%)
random value in [10:20] = 16
- /var/folders/l0/gs5hnkm56g54bmxg32r6nnwr0000gn/T/tmpwq345j63/tb.sv:14: Verilog $finish