Process Control: join_any, join_none, disable fork
Testbenches run many things at once — driving, monitoring, timing out. SystemVerilog’s fork...join variants and fine-grained process control are how you express and manage that concurrency.
join, join_any, join_none
join waits for all forked branches; join_any continues after the first finishes; join_none continues immediately, leaving the branches running. The classic use is a timeout: race the real work against a watchdog with join_any, then disable fork to kill the loser.
module tb;
task automatic do_work(int ns); #(ns); $display("work done at t=%0t", $time); endtask
initial begin
fork
do_work(20); // the real work
begin #35; $display("timeout fired at t=%0t", $time); end
join_any // continue when EITHER finishes
$display("join_any returned at t=%0t (work won)", $time);
disable fork; // kill the still-running timeout branch
#50 $display("ended cleanly, no late timeout print");
$finish;
end
endmodulework done at t=20 join_any returned at t=20 (work won) ended cleanly, no late timeout print - /var/folders/l0/gs5hnkm56g54bmxg32r6nnwr0000gn/T/tmpksrxcqvi/tb.sv:11: Verilog $finish
Check yourself
What is the difference between <code>join</code>, <code>join_any</code> and <code>join_none</code>?
join blocks until every forked branch completes. join_any unblocks as soon as the first branch completes (others keep running). join_none unblocks immediately, spawning the branches as background processes.
How do you implement a ‘first of work-or-timeout, then clean up’ pattern?
fork the work and a timed branch, join_any to proceed when either finishes, then disable fork to terminate whichever branch is still running so it can’t fire later.
Share your question in comments or talk to our mentor team for batch guidance.
Compile and simulate this in the browser — no install. Edit the code and re-run instantly.
Learn Verilog with mentors, labs and placement support
This free series is maintained by the ChipXpert training team in Hyderabad & Bengaluru. Go deeper with instructor-led courses on real EDA tools.
Explore VLSI Courses