cocotb: Python-Based Verification
cocotb is a Python framework for verifying HDL designs. Instead of writing the testbench in SystemVerilog, you write it in Python — coroutines drive and sample the DUT through a standard simulator, and the full Python ecosystem (models, data structures, libraries) is available for your reference model and stimulus. It is popular for its low boilerplate and fast ramp-up, and the ChipXpert Verification Lab runs cocotb in the browser.
A cocotb test
A cocotb test is an async function decorated with @cocotb.test(). You await clock edges and timers, assign to DUT signals through the dut handle, and assert on results in plain Python:
import cocotb
from cocotb.triggers import RisingEdge, Timer
from cocotb.clock import Clock
import random
@cocotb.test()
async def test_adder(dut):
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
for _ in range(100):
a, b = random.randint(0, 15), random.randint(0, 15)
dut.a.value = a
dut.b.value = b
await RisingEdge(dut.clk)
await Timer(1, units="ns")
assert dut.sum.value == a + b, f"{a}+{b} gave {int(dut.sum.value)}"
dut._log.info("100 random adds checked OK")The mental model is identical to a SystemVerilog testbench — generate, drive, sample, check — but expressed in Python coroutines. cocotb drives the same open-source simulators (Icarus, Verilator) underneath, which is exactly what the ChipXpert Verification Lab exposes: paste this test, point it at the DUT, and run it in the browser.
Check yourself
How does a cocotb test drive and sample the DUT?
Through the dut handle in an async function: assign to signals with dut.sig.value = x, and advance time by awaiting triggers like RisingEdge(dut.clk) or Timer(…). Checks are plain Python asserts. cocotb runs on top of a standard HDL simulator.
What is the main advantage of cocotb over a SystemVerilog testbench?
You write the testbench in Python, so reference models, randomisation and data handling use the full Python ecosystem with far less boilerplate, and it runs on free simulators. The trade-off is that it is not the industry-standard UVM used in most large ASIC flows.
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