Constrained-Random Verification (CRV)

Constrained-random verification (CRV) is the engine of modern verification. Instead of hand-writing stimulus, you declare random variables and constraints that bound them to the legal, interesting space — then let the solver generate endless valid scenarios. The skill is writing constraints that are neither too loose (illegal stimulus) nor too tight (missed corners).

Randomize with constraints

A transaction class marks fields rand and adds constraint blocks; calling randomize() asks the solver for a legal assignment. The canonical form (shown for reference — full constraint solving needs a SystemVerilog simulator; run it in the ChipXpert Verification Lab):

class BusTxn;
  rand bit [31:0] addr;
  rand bit [7:0]  len;
  rand bit        is_write;

  constraint c_addr  { addr % 4 == 0;            // word-aligned
                       addr inside {[32'h0:32'hFFF]}; }
  constraint c_len   { len inside {[1:16]};      // burst 1..16
                       len dist {1:=50, [2:16]:/50}; }  // 50% single beats
endclass

initial begin
  BusTxn t = new();
  repeat (1000) begin
    assert(t.randomize());                        // solver picks a legal txn
    drive(t);                                     // every one is legal + varied
  end
end

Key ideas: inside bounds a set/range, dist weights the distribution, solve a before b orders dependent variables, and an implication (a -> {b}) makes one field depend on another. The same constraints that keep stimulus legal also steer it toward hard-to-reach corners.

The idea is provable with weighted randomisation the browser simulator runs — this generates a legal, aligned, weighted address stream and proves every value satisfies the constraint:

module tb;
  int aligned_ok = 1;
  initial begin
    for (int i = 0; i < 2000; i++) begin
      bit [31:0] addr = {$urandom_range(0, 'h3FF), 2'b00};  // force word-aligned in 0..0xFFF
      if (addr[1:0] != 0 || addr > 32'hFFF) aligned_ok = 0; // check the "constraint"
    end
    $display("2000 constrained addresses: all word-aligned & in range = %s",
             aligned_ok ? "YES (constraint held)" : "NO");
    $finish;
  end
endmodule

2000 constrained addresses: all word-aligned & in range = YES (constraint held)
- /var/folders/l0/gs5hnkm56g54bmxg32r6nnwr0000gn/T/tmpkyb6vvk6/tb.sv:10: Verilog $finish

Check yourself

What does the <code>dist</code> operator add over plain <code>inside</code>?

inside only makes values legal (uniform within the set). dist weights the probability distribution, e.g. len dist {1:=50, [2:16]:/50} makes single-beat bursts far more likely — so realistic traffic emerges instead of a flat distribution.

What is the risk of constraints that are too loose vs too tight?

Too loose generates illegal stimulus the DUT was never meant to handle, producing false failures. Too tight shrinks the random space so corner cases are never reached, letting real bugs hide. Good constraints bound exactly the legal space and bias toward interesting regions.

Have questions about this topic?
Share your question in comments or talk to our mentor team for batch guidance.

Need Fee, Duration, or Demo Class Details?

Talk to our admin team for the latest batch plan and career guidance.

Contact Admin Team

▶ Try it in the ChipXpert Lab

Compile and simulate this in the browser — no install. Edit the code and re-run instantly.

Open in Verification Lab

Learn Verilog with mentors, labs and placement support

This free series is maintained by the ChipXpert training team in Hyderabad & Bengaluru. Go deeper with instructor-led courses on real EDA tools.

Explore VLSI Courses