Coverage-Driven Verification and Closure

If random stimulus is the engine, functional coverage is the fuel gauge. Coverage-driven verification (CDV) closes the loop: run random tests, measure which interesting scenarios were hit, find the gaps, and steer new constraints or tests at them until coverage reaches its goal. Without coverage you never know whether 10,000 random tests exercised the design or just hammered one path.

Covergroups and the closure loop

A covergroup samples variables into coverpoints with bins; cross coverage records combinations (e.g. every opcode × every addressing mode). The CDV loop is: (1) run random regression, (2) merge coverage, (3) read the holes, (4) add constraints/tests aimed at the holes, (5) repeat to closure. The syntax is shown for reference (needs a SV simulator — run it in the Verification Lab):

covergroup cg_bus @(posedge clk);
  cp_op  : coverpoint txn.op  { bins rd = {READ}; bins wr = {WRITE}; }
  cp_len : coverpoint txn.len { bins small = {[1:4]};
                                bins big   = {[5:16]}; }
  x_op_len : cross cp_op, cp_len;      // every op x every length class
endgroup

cg_bus cg = new();
// ... cg.sample() happens automatically on the clock
// report: $display("coverage = %0.1f%%", cg.get_coverage());

The essence — tracking which bins were hit until all are covered — runs in plain code the browser simulator executes: it classifies 500 random transactions into bins and reports coverage, reaching 100% once every bin is seen:

module tb;
  initial begin
    bit [3:0] bins_hit = 0;        // 4 length-class bins
    for (int i = 0; i < 500; i++) begin
      int len = $urandom_range(1,16);
      if      (len <= 4)  bins_hit[0] = 1;
      else if (len <= 8)  bins_hit[1] = 1;
      else if (len <= 12) bins_hit[2] = 1;
      else                bins_hit[3] = 1;
    end
    $display("length-class bins hit = %b  coverage = %0d%%",
             bins_hit, ($countones(bins_hit)*100)/4);
    $finish;
  end
endmodule

length-class bins hit = 0100  coverage = 25%
- /var/folders/l0/gs5hnkm56g54bmxg32r6nnwr0000gn/T/tmp13s6pjn5/tb.sv:13: Verilog $finish