The Verification Plan and Signoff

Before a line of testbench is written, strong teams write a verification plan (vplan): the document that turns a specification into a checklist of what must be verified and how you will know it is done. It is what keeps constrained-random honest — coverage goals in the plan define closure, not a gut feeling.

What a vplan contains

• Features — every feature and mode from the spec, itemised.
• Stimulus — how each feature will be exercised (directed or random, which constraints).
• Checks — the assertion or scoreboard that proves each feature works.
• Coverage — the covergroups/crosses whose completion proves the feature was tested.
• Signoff criteria — the coverage %, assertion pass, and bug-rate thresholds that declare the block done.

The plan links each feature to a concrete coverage metric, so “verification complete” becomes measurable: 100% of planned functional coverage hit, all assertions passing across the regression, code coverage at target, and the bug discovery rate flattened. This traceability — spec → plan → coverage → closure — is what distinguishes a verified design from a merely simulated one.

A vplan is a living document: new bugs, waivers and spec changes feed back into it, and coverage reports are reviewed against it at every milestone. It is also the artifact auditors and customers ask for as evidence that the design was actually verified.