Scoreboards and Reference Models

The scoreboard is where correctness is decided. It holds an independent reference model of what the DUT should do, and compares the DUT’s actual output against the model’s prediction for every transaction. If the two ever disagree, the test fails — that is the entire point of the environment.

Reference model and matching

For pipelined or out-of-order DUTs the scoreboard must also handle ordering: it often queues expected results and matches each DUT output against the oldest outstanding prediction. The example implements a queue-based scoreboard around a DUT with latency — expected values are pushed when stimulus is issued and popped/compared when the DUT produces a result:

module tb;
  // DUT: squares its input, 1-cycle latency
  reg clk=0; reg [7:0] in; reg in_v;
  reg [15:0] out; reg out_v;
  always #5 clk=~clk;
  always @(posedge clk) begin out <= in*in; out_v <= in_v; end

  // scoreboard: queue of expected results
  reg [15:0] expq [$]; integer errors = 0, checked = 0;
  always @(posedge clk) begin
    if (in_v)  expq.push_back(in*in);                 // predict on issue
    if (out_v) begin                                  // check on result
      reg [15:0] e; e = expq.pop_front();
      checked = checked + 1;
      if (out !== e) begin errors=errors+1; $display("SB FAIL got=%0d exp=%0d", out, e); end
    end
  end

  integer i;
  initial begin
    in_v=0;
    for (i=1;i<=8;i=i+1) begin @(negedge clk); in=i; in_v=1; end
    @(negedge clk); in_v=0;
    repeat(3) @(posedge clk);
    $display("scoreboard checked %0d results, errors=%0d %s", checked, errors, errors?"FAIL":"PASS");
    $finish;
  end
endmodule

scoreboard checked 8 results, errors=0 PASS
- /var/folders/l0/gs5hnkm56g54bmxg32r6nnwr0000gn/T/tmpf60bzulj/tb.sv:26: Verilog $finish

Check yourself

Why must the scoreboard’s reference model be independent of the DUT’s RTL?

If the checker reused the DUT’s own logic, a bug in that logic would appear in both the actual and expected results and cancel out, so the test would pass despite being wrong. An independent model (written from the spec, often at a higher abstraction) can disagree with a buggy DUT and expose it.

How does a scoreboard handle a DUT with latency or pipelining?

It decouples prediction from checking: expected results are pushed into a queue when stimulus is issued and popped to compare when the DUT eventually produces each output. For out-of-order DUTs it matches by tag/ID rather than strict FIFO order.

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